User's Manual

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GPIO[10] ]/UART_RTS
UART_CTSn (input)
I
VIO
*37
PCIE_RX_N/USB3_RX_N*
PCI Express Receive Data—Negative / USB 3.0 RX_N*
I
VIO
38
NC
NC
39
GND
System Ground Pin
40
NC
NC
*41
PCIE_TX_P/USB 3_TX_P*
PCI Express Transmit Data—Positive / USB 3.0 TX_P*
O
VIO
*42
BT_WAKE*
Host to UART_BT wake up*
I
VIO
*43
PCIE_TX_N/USB 3_TX_N*
PCI Express Transmit Data—Negative / USB 3.0 TX_N*
O
VIO
44
COEX3
NC
45
GND
System Ground Pin
46
COEX2
NC
47
PCIE_RCLK_P
PCI Express Differential Clock Input—Positive
I
VIO
48
COEX1
NC
49
PCIE_RCLK_N
PCI Express Differential Clock Input—Negative
I
VIO
50
SLP_CLK
32.768KHz external clock
I
VIO
51
GND
System Ground Pin
52
PCIE_PERST_N
PCIe host indication to reset the device (input) (active low)
I
VIO
53
PCIE_CLKREQn
PCIe clock request (input/output) (active low)
I/O
VIO
*54
GPIO[1]/PDn*
USB_VBUS_ON power valid indication/ PDn (optional)*
I
VIO
55
PCIE_WAKEn
PCIe wake signal (output) (active low)
O
VIO
56
PCIE_DISABLE_N
PCIe host indication to disable the WLAN function of the device
I
VIO
57
GND
System Ground Pin
58
NC
NC
59
Reserved
NC
60
NC
NC
61
Reserved
NC
62
NC
NC
63
GND
System Ground Pin
64
NC
NC
I
65
NC
NC
I
66
NC
NC
67
NC
NC
I
68
NC
NC
69
GND
System Ground Pin
70
NC
NC
71
NC
NC
72
3.3V
3.3V VBAT system power supply input
I
VIO
73
NC
NC