Data Sheet

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9. GENERAL LAYOUT GUIDELINES
Follow these guidelines to obtain good signal integrity and avoid EMI:
1. Place components and route signals using the following design practices:
• Keep analog and digital circuits in separate areas.
• Identify all high-bandwidth signals and their return paths. Treat all critical signals as current
loops. Check each critical loop area before the board is built. A small loop area is more
important than short trace lengths.
• Orient adjacent-layer traces so that they are perpendicular to one another to reduce crosstalk.
• Keep critical traces on internal layers, where possible, to reduce emissions and improve
immunity to external noise.
However, RF traces should be routed on outside layers to avoid the use of vias on these traces.
• Keep all trace lengths to a practical minimum. Keep traces, especially RF traces, straight
wherever possible. Where turns are necessary, use curved traces or two 45-degree turns.
Never use 90-degree turns.
2. Consider the following with respect to ground and power supply planes:
• Route all supply voltages to minimize capacitive coupling to other supplies. Capacitive
coupling can occur if supply traces on adjacent layers overlap. Supplies should be separated
from each other in the stack-up by a ground plane, or they should be coplanar (routed on
different areas of the same layer).
• Provide an effective ground plane. Keep ground impedance as low as possible. Provide as
much ground plane as possible and avoid discontinuities. Use as many ground vias as
possible to connect all ground layers together.
• Maximize the width of power traces. Verify that they are wide enough to support target
currents, and that they can do so with margin. Verify that there are enough vias if the traces
need to change layers.
3. Consider these power supply decoupling practices:
• Place decoupling capacitors near target power pins. If possible, keep them on the same side
as the IC they decouple to avoid vias that add inductance. If a filter component cannot be
directly connected to a given power pin with a very short and fat etch, do not connect it by a
copper trace. Instead, make the connection directly to the associated planes using vias.
• Use appropriate capacitance values for the target circuit, and consider each capacitor's self-
resonant frequency.