Data Sheet
Table Of Contents
16
3.4.2.2 SDR12, SDR25, SDR50 Modes (up to 100MHz) (1.8V)
SDIO Protocol Timing Diagram - SDR12, SDR25, SDR50 Modes (up to 100 MHz)(1.8V)
Symbol Parameter Condition Min Typ Max Units
F
pp
CLK Frequency SDR12/25/50 25
-
100 MHz
T
CLK
Clock Time SDR12/25/50 10
-
40 ns
T
IS
Input Setup Time SDR12/25/50
3
-
-
ns
T
IH
Input Hold Time SDR12/25/50 0.8
-
-
ns
T
CR
,T
CF
Rise time, fail time
TCR ,TCF <2ns(max) at 100MHz
CCARD =10pF
SDR12/25/50
-
-
0.2*T
CLK
ns
T
ODLY
Output Delay Time
CL ≦ 30pF
SDR12/25/50
-
-
7.5 ns
T
OH
Output Hold Time
CL =15pF
SDR12/25/50 1.5
-
-
ns
SDIO Timing Data - SDR12/25/50 modes. (1.8V)