User`s manual

BIOS SETUP

Advanced Chipset Features

This Setup menu controls the configuration of the chipset.

Advanced Chipset Features

DRAM Clock Host CLK ITEM HELP

DRAM Timing By SPD Disabled Menu Level

SDRAM Cycle Length 3

Bank Interleave Disabled

Memory Hole Disabled

P2C/C2P Concurrency Enabled

Fast R-W Turn Around Enabled

System BIOS Cacheable Disabled

Video BIOS Cacheable Disabled

Frame Buffer Size 8M

AGP Aperture Size 64M

OnChip USB Enabled

USB Keyboard Support Disabled

OnChip Sound Enabled

CPU to PCI Write Buffer Enabled

PCI Dynamic Bursting Enabled

PCI Master 0 WS Write Enabled

PCI#2 Access #1 Retry Disabled

AGP Master 1 WS Write Disabled

AGP Master 1 WS Read Disabled

DRAM Clock

This setting sets the DRAM clock frequency. The default sets it based on

the Host CPU clock (front side bus).

DRAM Timing by SPD

This field sets the DRAM Timing based on SPD. The default setting is

Disabled.

SDRAM Cycle Length

This feature is similar to SDRAM CAS Latency Time. It controls the

time delay (in clock cycles - CLKs) that passes before the SDRAM starts

to carry out a read command after receiving it. This also determines the

number of CLKs for the completion of the first part of a burst transfer.

Thus, the lower the cycle length, the faster the transaction. However,

some SDRAM cannot handle the lower cycle length and may become

unstable. So, set the SDRAM Cycle Length to 2 for optimal performance

if possible but increase it to 3 if your system becomes unstable.

Bank Interleave

This decides how multiple memory modules communicate. Enable or

Disable this. It will only make a difference if you have more than one

memory module.