Service manual

1-8 Description: Functional Theory of Operation
The modulated RF signal is amplified by the Driver/Final Module and is output to the site transmit
antenna via a circulator and a harmonic filter/coupler. During excessive output VSWR, the ratio of
the forward and reflected voltages from the directional coupler may be used to reduce, or turn off, the
transmitter power. Additional circuitry is also provided to reduce output power during excessive
current drain and high temperature conditions, and to control the fan.
See Figure 1-6 for the Power Amplifier block diagram.
1.3.2 Receiver Circuitry Operation
1.3.2.1 Introduction
The Receiver Circuitry accepts receive RF signals from the site receive antenna, performs filtering
and dual conversion, and outputs a digitized receive signal to the SCM. The receiver module utilized
has an on-board preselector.
1.3.2.2 Receiver Module Operation
The receive signal is input from the site receive antenna to the receiver module, or to an external
preselector filter (a separate assembly attached to the rear of the base station/repeater which
provides highly selective bandpass filtering). The signal is fed through a low-pass filter, varactor-
tuned preselector (VHF/UHF)/fixed preselector (800/900 MHz), RF amplifier and image filter to the
RF input of the first mixer. The filtered signal is mixed with an injection signal generated by the
receive synthesizer/VCO, resulting in a first i-f (intermediate frequency) signal. The injection signal
frequency is determined by frequency programming data from the SCM via the SPI bus. The specific
frequency of the first i-f depends on the frequency band of the base station/repeater.
The first i-f signal is filtered and input to a custom receiver IC. This component contains circuitry for
generating the second injection signal, mixing down the first i-f to 2.25 MHz, amplification and A/D
(analog-to-digital) conversion of the second i-f signal, resulting in a digitized receive signal. This
signal is fed as differential data to the SCM.
See Figure 1-3 for the Receiver block diagram.