User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 99
UG380 (v2.7) October 29, 2014
Configuration Packets
FAR_MAJ Register
Frame Address Register sets the starting block and column address for the next
configuration data input. See Table 5-31.
FAR_MIN Register
.
There are three types of write to FAR:
• Write one word to FAR_MAJ: only updates the FAR_MAJ.
• Write one word to FAR_MIN: only updates the FAR_MIN.
• Write two words to FAR_MAJ: updates both FAR_MAJ and FAR_MIN; the data for
FAR_MAJ will come first.
FDRI Register
Configuration data is written to the device by loading the command register with the
WCFG command and then loading the Frame Data Input Register.
FDRO Register
The FDRO is for reading configuration data or captured data from the device. Loading the
command register with the RCFG command, and then addressing the FDRO with a read
command perform a readback.
MASK Register
MASK register performs writes to the CTL register. A 1 in bit N of the mask allows that bit
position to be written in the CTL register. The default value of the mask is 0.
EYE_MASK Register
The EYE_MASK register stores the mask for the SCP pins for the Multi-Pin Wake-Up
feature. It is 16 bits, with the lower 8 representing the mask. The upper 8 bits are reserved.
The lower 8 bits are set from the -g wakeup_mask BitGen option.
LOUT Register
The Legacy Output Register (LOUT) is used for daisy-chaining the configuration bit
stream to other Xilinx devices. Data written to the LOUT is serialized and appears on the
DOUT pin.
Table 5-31: Frame Address Register (MAJOR)
BLK ROW MAJOR
Bits [15:12] [11:8] [7:0]
0xxx xxxx xxxxxxxx
Table 5-32: Frame Address Register (MINOR)
Block RAM (Reserved) MINOR
Bits [15:14] [13:10] [9:0]
xx 0000 xxxxxxxxxx