User guide

98 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
CRC Register
The Cyclic Redundancy Check register utilizes a standard 32-bit CRC checksum algorithm
to verify bitstream integrity during configuration. If the value written matches the current
calculated CRC, the CRC_ERROR flag is cleared and startup is allowed.
LOUT W 6'h09 Legacy output for serial daisy-chain.
COR1 R/W 6'h0a Configuration Option 1.
COR2 R/W 6'h0b Configuration Option 2.
PWRDN_REG R/W 6'h0c Power-down Option register.
FLR W 6'h0d Frame Length register.
IDCODE R/W 6'h0e Product IDCODE.
CWDT R/W 6'h0f Configuration Watchdog Timer.
HC_OPT_REG R/W 6'h10 House Clean Option register.
CSBO W 6'h12 CSB output for parallel daisy-chaining.
GENERAL1
R/W 6'h13
Power-up self test or loadable program
address.
GENERAL2 R/W 6'h14 Power-up self test or loadable program
address and new SPI opcode.
GENERAL3 R/W 6'h15 Golden bitstream address.
GENERAL4 R/W 6'h16 Golden bitstream address and new SPI
opcode.
GENERAL5 R/W 6'h17 User-defined register for fail-safe scheme.
MODE_REG R/W 6'h18 Reboot mode.
PU_GWE W 6'h19 GWE cycle during wake-up from suspend.
PU_GTS W 6'h1a GTS cycle during wake-up from suspend.
MFWR W 6'h1b Multi-frame write register.
CCLK_FREQ W 6'h1c CCLK frequency select for master mode.
SEU_OPT R/W 6'h1d SEU frequency, enable and status.
EXP_SIGN
R/W 6'h1e
Expected readback signature for SEU
detection.
RDBK_SIGN
W 6'h1f
Readback signature for readback command
and SEU.
BOOTSTS R 6'h20 Boot History Register.
EYE_MASK R/W 6'h21 Mask pins for Multi-Pin Wake-Up.
CBC_REG W 6'h22 Initial CBC Value Register.
Table 5-30: Configuration Registers (Cont’d)
Register Name R/W Address Description