User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 95

UG380 (v2.7) October 29, 2014

Configuration Memory Frames

Spartan-6 FPGA configuration memory is arranged in frames that are tiled about the

device. Because these frames are the smallest addressable segments of the Spartan-6 FPGA

configuration memory space, all operations must act upon whole configuration frames.

Most frames are 65 words of 16 bits. Spartan-6 FPGA frame counts are shown in Table 5-22.

Depending on BitGen options, additional overhead exists in the configuration bitstream.

The exact bitstream length is available in the rawbits file (.rbt) created by using the -b

option with BitGen or selecting Create ASCII Configuration File in the Generate

Programming File options popup in ISE software. Bitstream length (words) are roughly

equal to the configuration array size (words) plus configuration overhead (words).

Bitstream length (bits) are roughly equal to the bitstream length in words times 16.

There are three types of configuration frames. These frame types contain data for specific

segments of the FPGA:

• Type 0: Core: CLB, DSP, input/output interconnect (IOI), clocking

•Type 1: BlockRAM

• Type 2: IOB

Table 5-22: Frame Counts

Device

Number of Type 0

Frames for Core

Block RAM

Columns

Number of Type 1

Frames for Block RAM

Number of

I/Os

(1)

Length of Type 2

Frames for IOB

6SLX4 2028 1 37,440 132 897

6SLX9 2028 2 37,440 200 897

6SLX16 2976 2 37,440 232 1,073

6SLX25 5065 3 70,200 266 1,153

6SLX25T 5065 3 70,200 266 1,153

6SLX45 9088 4 149,760 358 1,577

6SLX45T 9088 4 149,760 370 1,577

6SLX75 15384 4 224,640 426 1,801

6SLX75T 15384 4 224,640 426 1,801

6SLX100 20304 6 336,960 498 2,089

6SLX100T 20304 6 336,960 498 2,089

6SLX150 27240 6 336,960 576 2,401

6SLX150T 27240 6 336,960 576 2,401

Notes:

1. I/O count can be greater than in available packages due to unbonded I/O.