User guide

94 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
JTAG Instructions
eFUSE registers can be read through JTAG ports. eFUSE programming can be done only
via JTAG. Table 5-20 lists eFUSE-related JTAG instructions. Refer to Chapter 10, Advanced
JTAG Configurations, for general JTAG communication protocol. These instructions are
not sufficient to program eFUSEs. A precise algorithm is used and not provided. The only
supported method of programming eFUSEs is by using the iMPACT software.
V
FS
Pin
In Spartan-6 devices, the V
FS
pin is one of two pins dedicated to eFUSE operation. The V
FS
pin should be treated as a power supply pin for testing purposes, such as power-up ramp
and ESD stress.
The voltage specification for the V
FS
pin during programming is 3.3V nominal. The supply
must be able to provide up to 40 mA of current during programming. For read mode, the
V
FS
pin only needs to be lower than the V
CCAUX
maximum operating condition. See
Table 5-21 for V
FS
bias conditions. For the full specification, see DS162, Spartan-6 FPGA
Data Sheet: DC and Switching Characteristics.
RFUSE Pin
The RFUSE pin is the second dedicated pin for eFUSE operation. If programming the
eFUSE is required, connect a 1,140Ω resistor to ground. If a 1,140Ω resistor is difficult to
acquire, it can be replaced with an 1,130Ω resistor in series with a 10Ω resistor. Resistor
tolerance can be found in DS162
, Spartan-6 FPGA Data Sheet: DC and Switching
Characteristics. When not programming or using eFUSE, it is recommended to connect
RFUSE to V
CCAUX
or GND, or RFUSE can float.
V
CCAUX
Pin
The V
CCAUX
must be equal to or greater than V
FS
when programming the eFUSE. V
CCAUX
can be any of the other recommended operating values allowed in DS162
, Spartan-6 FPGA
Data Sheet: DC and Switching Characteristics, when reading or configuring from the eFUSE.
Table 5-20: eFUSE-Related JTAG Instructions
JTAG Instruction Code Action
FUSE_KEY
6'h3B
Selects the 256-bit FUSE_KEY register.
FUSE_OPTION
6'h3C
Selects the 16-bit FUSE_OPTION register for data
and commands for interfacing with eFUSE.
ISC_FUSE_READ
6'h30
Selects the DNA eFUSE registers. Must be preceded
by ISC_ENABLE and followed by ISC_DISABLE.
FUSE_UPDATE
6'h3A
Updates the FPGA with the values from the AES
and CNTL eFUSEs.
FUSE_CNTL
6'h34
Selects the 32-bit FUSE_CNTL register.
Table 5-21: V
FS
Pin Bias Conditions
eFUSE Mode V
FS
Pin Bias
Read or Unused V
CC
or GND (recommended)
Program 3.3V