User guide

88 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
In a Slave configuration mode, additional clocks are needed after DONE goes High to
complete the startup events. In Master configuration mode, the FPGA provides these
clocks. The number of clocks necessary varies depending on the settings selected for the
startup events. A general rule is to apply eight clocks (with DIN all 1’s) after DONE has
gone High. More clocks are necessary if the startup is configured to wait for the DCM and
PLLs to lock (LCK_CYCLE).
When using the external master clock (USERCCLK) pin, I/O standard becomes enabled at
the EOS phase. As I/O standard changes from the default pre-configuration value to the
user specified value, a glitch might appear. It is recommended to use clock enables or a
reset to prevent glitches from affecting the design.
Table 5-17: Signals Relating to the Startup Sequencer
Signal Name Type Access
(1)
Description
DONE Bidirectional
(2)
DONE pin or
Spartan-6 FPGA
Status Register
Indicates configuration is complete. Can be held Low externally to
synchronize startup with other FPGAs.
GWE
Status
Spartan-6 FPGA
Status Register
Global Write Enable (GWE). When deasserted, GWE disables the CLB and
the IOB flip-flops as well as other synchronous elements on the FPGA.
GTS Global 3-State (GTS). When asserted, GTS disables all the I/O drivers
except for the configuration pins.
DCM_LOCK DCM_LOCK indicates when all DCMs and PLLs have locked. This signal
is asserted by default. It is active if the STARTUP_WAIT option is used on
a DCM and the LCK_CYCLE option is used when the bitstream is
generated.
Notes:
1. Information on the Spartan-6 FPGA status register is available in Table 5-35, page 102. Information on accessing the device status
register via JTAG is available in Table 6-5, page 122. Information on accessing the device status register via SelectMAP is available in
Table 6-1, page 117.
2. Open-drain output with internal pull-up by default; the optional driver is enabled using the BitGen DriveDone option.
3. GWE is asserted synchronously to the configuration clock (CCLK) and has a significant skew across the part. Therefore, sequential
elements might not be released synchronously to the system clock and timing violations can occur during startup. It is
recommended to reset the design after startup and/or apply some other synchronization technique.
X-Ref Target - Figure 5-12
Figure 5-12: Configuration Signal Sequencing (Default Startup Settings)
POR
INIT_B
DONE
GWE
GTS
EOS
CCLK
Initialization
Configuration
Startup
End of Bitstream
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