User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 85

UG380 (v2.7) October 29, 2014

Configuration Sequence

The Spartan-6 FPGA JTAG IDCODE register has the following format:

vvvv:fffffff:aaaaaaaaa:ccccccccccc1

where

v = revision

f = 7-bit family code

a = 9-bit array code (4-bit subfamily and 5-bit device identifier)

c = 11-bit company code

Table 5-13: ID Codes

Device ID Code (Hex)

6SLX4 0xX4000093

6SLX9 0xX4001093

6SLX16 0xX4002093

6SLX25 0xX4004093

6SLX25T 0xX4024093

6SLX45 0xX4008093

6SLX45T 0xX4028093

6SLX75 0xX400E093

6SLX75T 0xX402E093

6SLX100 0xX4011093

6SLX100T 0xX4031093

6SLX150 0xX401D093

6SLX150T 0xX403D093

Notes:

1. The X digit in the ID code corresponding to the four binary revision

bits are not used by the programming tools when performing

IDCODE verification.

Table 5-14: Signals Relating to the Device ID Check

Signal Name Type Access

(1)

Description

ID_Error Status Internal signal. Accessed only

through the

Spartan-6 FPGA

status register.

Indicates a mismatch between the

device ID specified in the bitstream

and the actual device ID.

Notes:

1. Information on the Spartan-6 FPGA status register is available in Tab le 5-35. Information on accessing

the device status register via JTAG is available in Table 6-5. Information on accessing the device status