User guide

80 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
Delaying Configuration
There are two ways to delay configuration for Spartan-6 devices:
• Hold the INIT_B pin Low during initialization. When INIT_B has gone High,
configuration cannot be delayed by subsequently pulling INIT_B Low.
• Hold the PROGRAM_B pin Low. The signals relating to initialization and delaying
configuration are defined in Table 5-10.
Configuration Sequence
While each of the configuration interfaces is different, the basic steps for configuring a
Spartan-6 device are the same for all modes. Figure 5-2 shows the Spartan-6 FPGA
configuration process. The following subsections describe each step in detail, where the
current step is highlighted in gray at the beginning of each subsection.
The Spartan-6 device is initialized and the configuration mode is determined by sampling
the mode pins in three setup steps.
Table 5-10: Signals Relating to Initialization and Delaying Configuration
Signal Name Type Access
(1)
Description
PROGRAM_B Input Externally accessible via the
PROGRAM_B pin.
Global asynchronous chip reset. Can be held Low to delay
configuration.
INIT_B Input,
Output,
or Open
Drain
Externally accessible via the
INIT_B pin.
Before the Mode pins are sampled, INIT_B is an input that
can be held Low to delay configuration.
After the Mode pins are sampled, INIT_B is an open-
drain, active-Low output that indicates whether a CRC
error occurred during configurati
on or a readback CRC
error occurred after configuration (when enabled)
:
0 = CRC error
1 = No CRC error (needs an external pull-up)
MODE_STATUS[1:0] Status Internal signals, accessible
through the
Spartan-6 FPGA
status register.
Reflects the direct pin value of the Mode pins.
Notes:
1. Information on the Spartan-6 FPGA status register is available in Table 5-38, page 104. Information on accessing the device status
register via JTAG is available in Table 6-5, page 122. Information on accessing the device status register via SelectMAP is available in
Table 6-1.
2. The Status type is an internal status signal without a corresponding pin.
X-Ref Target - Figure 5-2
Figure 5-2: Spartan-6 FPGA Configuration Process
Device
Power-Up
Sample Mode
Pins
Synchronization
Device ID
Check
CRC Check
Clear
Configuration
Memory
Startup
Sequence
Load
Configuration
Data
Start
Finish
UG380_c5_02_042909
Bitstream
Loading
Steps
123 45678
Setup