User guide

76 www.xilinx.com Spartan-6 FPGA Configuration User Guide

UG380 (v2.7) October 29, 2014

Chapter 5: Configuration Details

A Spartan-6 FPGA bitstream consists of two sections:

• Sync Word/Bus Width Auto Detection

• FPGA configuration

Sync Word/Bus Width Auto Detection

For parallel configuration modes, the bus width is auto-detected by the configuration

logic. A bus-width detection pattern uses the sync word. The configuration logic checks

the data received on the parallel bus. Depending on the byte sequence received, the

configuration logic can automatically switch to the appropriate external bus width.

Table 5-6 shows an example bitstream in x16 mode. When observing the pattern on the

FPGA data pin, the bits are bit swapped, as described in Parallel Bus Bit Order, page 79.

Bus-width auto detection is transparent to most users.

For the x8 bus, the configuration bus-width detection logic first finds 0xAA on the D[0:7]

pins, followed by 0x99. The logic then finds 0x55, and if 0x66 is found the next cycle,

then the device will continue in x8 mode. For the x16 bus, the configuration bus-width

detection logic checks the first byte to find 0x99 on D[0:7], followed by 0x66 the next clock

cycle because the rest of the sync word is on the upper bits. The device then continues on

6SLX45 11,939,296

6SLX45T 11,939,296

6SLX75 19,719,712

6SLX75T 19,719,712

6SLX100 26,691,232

6SLX100T 26,691,232

6SLX150 33,909,664

6SLX150T 33,909,664

Notes:

1. The bitstream length represents the typical default cases. Certain BitGen options can vary the bitstream

length, such as Compress. The x2 and x4 SPI configuration modes require additional commands and

will increase the bitstream length.

2. Bitstream lengths might appear to increase after the ISE tools, version 13.2. This is due to a software

change that affects designs containing 9K block RAMs. For more information on this change, refer to

the Block RAM Initialization section of UG383

, Spartan-6 FPGA Block RAM User Guide.

Table 5-5: Spartan-6 FPGA Bitstream Length (Cont’d)

Device Total Number of Configuration Bits

(1)

Table 5-6: Bus-Width Detection Pattern for x16 Data

D[8:15] D[0:7] Comments

0xFF 0xFF Pad word

0xAA 0x99 Sync word

0x55 0x66 Sync word

………