User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 63
UG380 (v2.7) October 29, 2014
Design Considerations
Configuring through Boundary-Scan
If the Spartan-6 device is configured via JTAG on power-up, any activity on the JTAG
signals will override the current configuration mode setting.
The configuration flow for Spartan-6 device configuration with JTAG is discussed in the
Chapter 10, Advanced JTAG Configurations. This chapter includes details about the
command sequences used for configuring a Spartan-6 device as a single device through
boundary-scan or as part of a multiple-device boundary-scan chain. A configured device
can be reconfigured by toggling the TAP and entering a CFG_IN instruction after pulsing
the PROGRAM_B pin or issuing the shut-down sequence. See Chapter 10, Advanced JTAG
Configurations.
Xilinx has proprietary programming cables (Parallel and USB) and boundary-scan
programming software (iMPACT) for prototyping purposes. These are not intended for
production environments but can be highly useful for verifying FPGA implementations
and JTAG chain integrity.
When trying to access other devices in the JTAG chain, it is important to know the size of
the instruction register length in order to shift in the correct number of leading 1s or 0s to
ensure each device receives the correct instructions. This information can be found in the
BSDL file for the device, provided in the ISE® software.
One of the most common boundary-scan vendor-specific instructions is the configure
instruction. If the Spartan-6 device is configured via JTAG, the configuration instructions
occur independent from the mode pins. Chapter 10, Advanced JTAG Configurations,
details device configuration through JTAG. The Spartan-6 FPGA JTAG configuration
algorithm uses the SVF-based flow, provided in XAPP058
, Xilinx In-System Programming
Using an Embedded Microcontroller.