User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 59
UG380 (v2.7) October 29, 2014
Chapter 3
Boundary-Scan and JTAG Configuration
Introduction
Spartan®-6 devices support IEEE Std 1149.1, defining Test Access Port (TAP) and
boundary-scan architecture. These standards ensure the board-level integrity of individual
components and the interconnections between them. In addition to connectivity testing,
boundary-scan architecture offers flexibility for vendor-specific instructions, such as
configure and verify, which add the capability of loading configuration data directly to
FPGAs and compliant PROMs. TAP and boundary-scan architecture is commonly referred
to collectively as JTAG.
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
The Spartan-6 family is fully compliant with the IEEE Std 1149.1 (TAP and boundary-scan
architecture). The architecture includes all mandatory elements defined in IEEE Std 1149.1.
These elements include the TAP, the TAP controller, the Instruction register, the instruction
decoder, the boundary-scan register, and the BYPASS register. The Spartan-6 family also
supports a 32-bit Identification register in full compliance with the standard. Outlined in
the following sections are the details of the JTAG architecture for Spartan-6 devices. More
details about the JTAG architecture for Spartan-6 devices can be found in Chapter 10,
Advanced JTAG Configurations.
Test Access Port (TAP)
The Spartan-6 FPGA TAP contains four mandatory dedicated pins as specified by the
protocol in Spartan-6 devices and in typical JTAG architecture (see Figure 10-1, page 158).
Three input pins and one output pin control the IEEE Std 1149.1 boundary-scan TAP
controller. Optional control pins, such as Test Reset (TRST), and enable pins might be
found on devices from other manufacturers. It is important to be aware of these optional
signals when interfacing Xilinx devices with parts from different vendors because they
might need to be driven.
The IEEE Std 1149.1 boundary-scan TAP controller is a state machine (16 states), shown in
Chapter 10, Advanced JTAG Configurations.