User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 57
UG380 (v2.7) October 29, 2014
Board Layout for Configuration Clock (CCLK)
Figure 2-25 shows a star topology where the transmission line branches to the multiple
CCLK inputs. The branch point creates a significant impedance discontinuity. This
arrangement is Not Recommended.
X-Ref Target - Figure 2-25
Figure 2-25: Not Recommended
Star Topology: One CCLK Output, Two CCLK Input
CCLK
Output
UG380_c2_24_042909
Z
0
Impedance
Discontinuity
Z
0
CCLK
Input 1
Z
0
CCLK
Input 2