User guide

UG380 (v2.7) October 29, 2014 www.xilinx.com Spartan-6 FPGA Configuration User Guide
06/27/2012 2.4 Updated bullet about V
BATT
being tied to V
CCAUX
or ground in notes 8, 17, 11, 15, and 17 after
Figure 2-3, Figure 2-6, Figure 2-7, Figure 2-12, and Figure 2-20 respectively. Updated notes after
Figure 2-13. Updated references in SPI Configuration Interface. Updated Master SPI Dual (x2)
and Quad (x4) Read Commands. In Master BPI Configuration Interface, updated support of
Spartan-6 FPGAs for parallel NOR flash from 512 Mb to 1 Gb and for iMPACT software to
program bottom boot parallel NOR flash. Updated note 2 after Figure 2-20. Replaced LVCMOS25
with LVCMOS in External Configuration Clock for Master Modes. Updated Board Layout for
Configuration Clock (CCLK).
Updated last paragraph of Providing Power.
Updated note 1 after Table 5-1. Updated descriptions of V
BATT
and V
FS
in Table 5-11. Added note
2 to Figure 5-4. Removed sentence about ID error from Check Device ID (Step 5). Updated
description of GTS startup setting after Table 5-16. Added note 3 to Table 5-17. Added SPI x1 to
Loading Encrypted Bitstreams. Updated first row of Table 5-21. Updated FAR_MAJ Register and
Boot History Status Register (BOOTSTS).
Updated first paragraph of Configuration Memory Read Procedure (SelectMAP).
Updated first paragraph of Status Register for Fallback and IPROG Reconfiguration.
Added CRC Masking. Added POST_CRC_SOURCE to Post_CRC Constraints.
Added paragraph about using SPI in a serial daisy-chain configuration to Serial Daisy-Chains.
Updated SelectMAP Reconfiguration.
01/23/2013 2.5 Updated first bullet in sixth paragraph in Overview. Added Vccaux Level. Removed “XC” from
some device references throughout the user guide. Updated Figure 2-2, Figure 2-6, Figure 2-21,
Figure 5-15, Figure 8-2, Figure 9-1, Figure 9-2, Figure 9-4, and Figure 9-5. Updated second
paragraph in SelectMAP Configuration Interface. Updated second paragraph in
Non-Continuous SelectMAP Data Loading. Updated sixth paragraph in Master BPI
Configuration Interface. Updated Table 2-7, Table 4-3, Table 5-2, Table 5-19, Table 5-50, Table 6-2,
Table 6-5, Table 6-6, and Table 10-4. Added Determining the Maximum Configuration Clock
Frequency. Updated first paragraph after Table 2-8. Updated third paragraph in Board Layout
for Configuration Clock (CCLK). Updated first paragraph in
FPGA I/O Pin Settings During
Configuration. Updated pin GCLK0 in Table 5-3. Updated second paragraph in Device
Power-Up (Step 1). Updated first paragraph in Cyclic Redundancy Check (Step 7). Updated first
paragraph in Startup (Step 8). Updated first and second paragraphs and Table 5-22 in
Configuration Memory Frames. Updated third paragraph in Frame Length Register. Updated
first paragraph in Identifier Memory Specifications. Updated Steps 3 and 6 in Configuration
Register Read Procedure (SelectMAP). Updated Step 13 in Configuration Memory Read
Procedure (SelectMAP). Updated first and sixth paragraphs following Figure 7-1. Updated first
paragraph and Table 7-4 in Status Register for Fallback and IPROG Reconfiguration. Added
Caution after first paragraph in Chapter 8, Readback CRC. Updated first and third bullet and
note in CRC Masking. Changed “dynamic” to “distributed” in CLB with LUT Configured as
Distributed RAM or Shift Register and in CLBs Near Top or Bottom IOI DRP with LUTs
Configured as Distributed RAM. Added second paragraph to Bit Sequence Boundary-Scan
Register.
06/20/2014 2.6 Updated first paragraph of CSI_B. Updated Figure 2-20. Updated explanation of O[15:0] in
Table 4-2. Updated SUSPEND pin in Table 5-2. Added Caution statement for Bit 16 in Table 5-19.
Added paragraph to the end of FPGA I/O Pin Settings During Configuration. Updated first
paragraph of Bitstream Overview. Updated Device Power-Up (Step 1). Updated second
paragraph of Bitstream Encryption. Updated second paragraph of Loading the Encryption Key.
Updated numbered procedure in Configuration Memory Read Procedure (SelectMAP). Added
explanation on how to carry out testing when the IOB is configured with an invertor in TAP
Controller and Architecture.
10/29/2014 2.7 Updated Steps 5 and 12 in Configuration Memory Read Procedure (SelectMAP). Updated Step
12 in Table 6-2. Minor update to Figure 10-3.
Date Version Revision