User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 41
UG380 (v2.7) October 29, 2014
SPI Configuration Interface
DIN/D0/
MISO/
MISO[1]
Input Master FPGA Serial Data Input and Slave
SPI flash output. Connect to the SPI flash
PROM’s Slave Data Output pin.
FPGA receives serial data
from PROM’s serial data
output.
User I/O
CSO_B Output Master SPI Chip Select Output.
Active Low. Connect to the SPI flash
PROM’s Slave Select input.
If HSWAPEN_B = 1,
connect this signal to V
CCO
through pull-up resistor
externally.
User I/O. Drive CSO_B High
after configuration to disable
the SPI flash and reclaim
MOSI, DIN, and CCLK pins.
Optionally reuse this pin,
MOSI, DIN, and CCLK to
continue communicating
with SPI flash.
CCLK Output Configuration Clock.
Generated by FPGA internal oscillator.
Connect to the SPI flash PROM’s Slave
Clock input.
Drive PROM’s clock input. User I/O. Drive High or Low
if not used.
DOUT Output Serial Data Output.
Used in multi-FPGA daisy-chain
configurations.
Not used in single-FPGA
designs; DOUT is pulled up
and is not actively driving.
In a daisy-chain
configuration, this pin
connects to the DIN input of
the next FPGA in the chain.
User I/O
INIT_B Open-Drain
Bidirectional
I/O
Initialization indicator.
Active Low. Goes Low at start of
configuration during initialization memory
clearing process. Released at the end of
memory clearing, where mode pins are
sampled.
Active during
configuration. If SPI flash
PROM requires more than
2 ms to awake after
powering on, hold INIT_B
Low until PROM is ready.
User I/O if POST_CRC is not
enabled. Use a pull-up
resistor on INIT_B.
DONE Open-Drain
Bidirectional
I/O
FPGA Configuration Done.
Low during configuration. Goes High when
the FPGA successfully completes
configuration.
Low indicates that the
FPGA is not yet configured.
Dedicated. Pulled High via
external pull-up. When
High, indicates that the
FPGA is successfully
configured.
PROGRAM_B Input Program FPGA.
Active Low. When asserted Low for 500 ns
or longer, forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting the
DONE and INIT_B pins after PROGRAM_B
returns High.
Must be High to allow
configuration to start.
Drive PROGRAM_B Low
and release to reprogram
FPGA. Hold PROGRAM_B
to force the FPGA I/O pins
into High-Z, allowing direct
programming access to SPI
flash PROM pins.
MISO[3:2] Input Master FPGA Serial Data Input and Slave
SPI data output.
Used only when using the
fast-read quad output
command.
User I/O
Table 2-6: Spartan-6 FPGA SPI Configuration Interface Pins (Cont’d)
Pin Name FPGA Direction Description During Configuration After Configuration