User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com UG380 (v2.7) October 29, 2014
02/22/2010 2.1 Changed the supported encryption data widths to x1 and x8 in the Bitstream Encryption section.
In the third paragraph of Loading Encrypted Bitstreams, clarified that the configuration
bitstream can be delivered in an x1 or x8 data width configuration mode, and indicated that SPI
x2 and x4, BPI x16, and SelectMAP x16 bus widths are not supported for encrypted bitstreams.
07/30/2010 2.2 Changed the value of pull-up resistors connected between DONE and VCCO_2 from 2.4 kΩ to
330Ω in Figure 2-2, Figure 2-3, Figure 2-6, Figure 2-7, Figure 2-12, and Figure 2-20. Changed the
value of the pull-up the resistor connected between INIT_B and VCCO_2 from 2.4 kΩ to 4.7 kΩ
in Figure 2-3 and Figure 2-6. Added ports RDWR_B and CSI_B to FPGA (tied to ground) in
Figure 2-6. Added second and third paragraphs about configuration clock frequency to Master
Modes. Added introductory sentence and two bullets about SelectMAP considerations to
SelectMAP Configuration Interface section. Added sentence about V
REF
to description of
RDWR_B in Table 2-3. Added sentence to first paragraph of CSI_B section indicating that CSI_B
should not be deasserted in the middle of a sync word. Reformatted the first paragraph in Master
BPI Configuration Interface into one paragraph followed by bullets, and added the bullet
indicating the removal of the BPI configuration interface from the XC6SLX25/T devices.
Changed “VCCO_0” to “VCCO_2” in Figure 2-22, Figure 2-23, and Figure 2-24. Changed second
paragraph in Providing Power section. Added “if Suspend feature is not used” and Note 4 to
Table 5-2. Changed table reference from Table 5-4 to Table 5-3 in first paragraph of Configuration
Pins section. Added “Dual-Purpose” to Table 5-3 title. Changed “LVCMOS25 8 mA SLOW” to
“LVCMOS 8 mA SLOW” in second paragraph of Device Power-Up (Step 1). Changed CCLK
Output Delay symbol in Table 5-12 from “T
ICCK
” to “T
BPIICCK
or T
SPIICCK
” and added Note 2.
Changed “V
POR
” to “the recommended operating voltage” in the paragraph following
Figure 5-4. Added fourth paragraph about startup waiting for DCMs and PLLs by assigning
the LCK_CYCLE option to
Startup (Step 8). Removed “DSP” from title in Figure 5-13. Added
third bullet to Bitstream Compression section under overall benefits on page 113. Changed
“warm boot” to “MultiBoot” in first paragraph of Fallback Behavior section. Added sentence
indicating how to generate the bitstream automatically to fourth paragraph of Fallback Behavior
section. Added last sentence to Note 2 in Table 7-1. Changed “DCM_WAIT” to “LCK_Cycle” in
Additional Memory Space Required for LCK_Cycle section title and text. Removed “66” from
the possible values listed in the description for the POST_CRC_FREQ constraint. Removed NCF
syntax examples from the Syntax Examples section. Changed “BPI UP” to “BPI” in Figure 9-4.
Changed “BPI UP, or BPI Down” to “or BPI“ in Note 7 (Notes relevant to Figure 9-4).
07/06/2011 2.3 Updated description of INIT_B in Table 2-2 and Table 2-3. Added VCCO_2 of 3.3V to Note 16 on
page 27, Note 9 on page 29, Note 18 on page 33, and Note 12 on page 35. Added a sentence about
deasserting the CSI_B signal to Non-Continuous SelectMAP Data Loading. Updated After
Configuration entries for CSO_B and INIT_B in Table 2-6. Updated Notes 11 and 16 on page 43.
Updated description of INIT_B in Table 2-7. Updated Note 2 on page 50, and Notes 11 and 18 on
page 51. Updated External Configuration Clock for Master Modes. Updated guideline about
configuration in master mode in Board Layout for Configuration Clock (CCLK).
Updated Note 2 after Table 5-3. In Table 5-5, updated Total Number of Configuration Bits
column and added Note 2. Removed -4 speed grade from paragraph before Table 5-11. Added
paragraph about external master clock pin after Table 5-17. Updated first paragraph of Bitstream
Encryption. Updated RFUSE Pin. Changed bitstream length from 32 to 16 and added list of three
types of configuration frames to Configuration Memory Frames. Removed Total Bits column
from Table 5-22. Updated Type 2 Packet. Changed direction of RDBK_SIGN in Table 5-30 from
R/W to W. Updated description of CRC_EXTSTAT_DISABLE in Table 5-34. Replaced type3
(PCFG) with type2 (IOB) in Frame Length Register. Added new paragraph before Table 5-41.
Updated Boot History Status Register (BOOTSTS) and Bitstream Compression.
Added readback limitations to Preparing a Design for Readback. Updated steps 7 and 8 in
Table 6-2. Removed AES encryption from MultiBoot Overview. Added Note 3 to Table 7-4.
Updated first sentence in second paragraph of page 137. Updated first paragraph of
POST_CRC_INIT_FLAG.
Updated Startup Sequencing (GTS).
Date Version Revision