User guide

34 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 2: Configuration Interface Basics
Microprocessor-Driven SelectMAP Configuration
For custom applications where a microprocessor or CPLD is used to configure a single
Spartan-6 device, either Master SelectMAP mode (use CCLK from the FPGA) or Slave
SelectMAP mode can be used (Figure 2-7). Slave SelectMAP mode is preferred. See
XAPP502
, Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP
Mode, for information on configuration from a microprocessor).
Notes relevant to Figure 2-7:
1. See Table 5-2, page 72 for internal pin terminations and pins affected by HSWAPEN.
2. DOUT/BUSY is an output that can drive during configuration and readback
operations.
X-Ref Target - Figure 2-7
Figure 2-7: Single-Device Slave SelectMAP Configuration from Microprocessor and CPLD
PROGRAM_B
SELECT
CLOCK
PROGRAM_B
INIT_B
DONE
VCCINT
VCCAUX
CSO_B
INIT _
B
CSI_B
PROGRAM_B
DONE
GND
VCCO _
2
M1
M0
HSWAPEN
VCCO _
0
CCLK
D[15:0]
VCCO
_0
RDWR _B
VCCO_2
.
VCC
VCCO_2
VCCO_2
GND
Configuration
Memory
Source
TMS
TDO
TCK
TDI
VREF
TMS
TCK
TDO
TDI
N.C.
N.C.
14
1
Xilinx Cable Header
(JTAG Interface)
4.7 kΩ
UG380_c2_07_062910
Spartan-6
FPGA
Microprocessor
or CPLD
D[15:0]
READ/WRITE
VCCO_2
VCCO_2
BUSY
4.7 kΩ
330Ω
VCCAUX
VCCAUX
Refer to the Notes following this figure for related information.
VFS
VBATT
VFS
VBATT
SUSPEND