User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 27
UG380 (v2.7) October 29, 2014
Serial Configuration Interface
5. The Spartan-6 FPGA VCCO_2 supply input and the Platform Flash PROM V
CCO
supply input must be the same voltage.
6. The DONE pin is by default an open-drain output with an internal pull-up. An
additional external pull-up is recommended. The DONE pin has a programmable
active driver that can be enabled via the BitGen option -g DriveDone.
7. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
recommended.
8. The BitGen startup clock setting must be set for CCLK for serial configuration, which
is done by default in the software. See UG628
, Command Line Tools User Guide for
details.
9. The PROM in this diagram represents one or more Xilinx PROMs. Multiple Xilinx
PROMs can be cascaded to increase the overall configuration storage capacity, further
described in UG161
, Platform Flash PROM User Guide.
10. The BIT file must be reformatted into a PROM file before it can be stored on the Xilinx
PROM. Refer to the Generating PROM Files, page 77, which outlines how to use
iMPACT software to generate the required files.
11. On some Xilinx PROMs, the reset polarity is programmable. RESET
should be
configured as active Low when using this setup.
12. Master Serial mode configuration is specific to the Platform Flash XCFS and XCFP
PROM only.
13. Unused configuration pins such as CSI_B and RDWR_B can be left floating or tied to
GND because they are not connected to any configuration logic in this mode. CSI_B
and RDWR_B are dual-purpose pins.
14. V
FS
is present in 6SLX75/T, 6SLX100/T, and 6SLX150/T devices, and is used for
eFUSE programming. See eFUSE, page 91 for more details.
15. V
BATT
is present in 6SLX75/T, 6SLX100/T, and 6SLX150/T devices, and is the power
source for AES key storage. If AES encryption is unused, V
BATT
can be tied to either
V
CCAUX
or ground, or can be left unconnected.
16. If VCCO_2
is 1.8V, V
CCAUX
must be 2.5V. If VCCO_2 is 2.5V or 3.3V, V
CCAUX
can be
either 2.5V or 3.3V.
17. The SUSPEND pin should be Low during power up and configuration. If the Suspend
feature is not used, the SUSPEND pin must be connected to ground.
Slave Serial Configuration
Slave Serial configuration is typically used for devices in a serial daisy-chain or when
configuring a single device from an external microprocessor or CPLD (see Figure 2-3).
Design considerations are similar to Master Serial configuration except for the direction of
CCLK. CCLK must be driven from an external clock source, which also provides data (see
Serial Configuration Data Timing, page 29).