User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 25
UG380 (v2.7) October 29, 2014
Serial Configuration Interface
Table 2-2 describes the serial configuration interface.
Table 2-2: Spartan-6 FPGA Serial Configuration Interface Pins
Pin Name Type
Dedicated
or Dual-
Purpose
Description
M[1:0] Input Dual-
Purpose
Mode Pins – determine configuration mode (see
Table 2-1).
CCLK Input or
Output
Dual-
Purpose
Configuration clock source for all configuration
modes except JTAG (see Design Considerations,
page 62).
DIN Input Dual-
Purpose
Serial configuration data input, synchronous to
rising CCLK edge.
DOUT Output Dual-
Purpose
Serial data output for downstream daisy-chained
devices. Data provided on the falling edge of
CCLK.
DONE Bidirectional,
Open-Drain,
or Active
Dedicated Active-High signal indicating configuration is
complete:
0 = FPGA not configured
1 = FPGA configured
Refer to the BitGen section of
UG628, Command
Line Tools User Guide
for software settings.
INIT_B Input or
Output,
Open-Drain
Dual-
Purpose
Before the Mode pins are sampled, INIT_B is an
input that can be held Low to delay configuration.
After the Mode pins are sampled, INIT_B is an
open-drain active-Low output indicating whether
a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
When the SEU detection function is enabled,
INIT_B is reserved and cannot be used as user
I/O.
PROGRAM_B Input Dedicated Active-Low asynchronous full-chip reset.