User guide

22 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 1: Configuration Overview
Loading Multiple FPGAs with the Same Configuration Bitstream
Generally, there is one configuration bitstream image per FPGA in a system. Multiple,
different FPGA bitstream images can share a single configuration PROM by leveraging a
configuration daisy-chain. However, if all the FPGAs in the application have the same part
number and use the same bitstream, only a single bitstream image is required. An
alternative solution, called a ganged configuration, loads multiple, identical FPGAs with
the same bitstream.
Configuration Factors
Many factors determine which configuration solution is optimal for a system and many
details need to be considered. Proper configuration mitigates problems later in the design
cycle.
Designers need to understand the difference between dedicated configuration pins and
reusable post configuration pins. Details can be found in the configuration details section.
Other issues that need to be considered are Data File formats and bitstream sizes. The size
of the bitstream is directly affected by the device size and there are several formats in
which the bitstream can be created.
The FPGA goes through certain sequences during the configuration process, from clearing
internal memory to activating the I/Os. This process is called the configuration sequence.
Designers should be aware of this sequence and its subsequences to understand the timing
from power-on to completed FPGA configuration and start-up.
The Spartan-6 LX75, LX75T, LX100, LX100T, LX150, and LX150T FPGAs also have
enhanced security features such as AES encryption. This feature is very useful in
protecting bitstream theft.
More details can be found in Chapter 5, Configuration Details.