User guide

20 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 1: Configuration Overview
and broad interoperability. It is important to consider the link activation time in the PCI
application and ensure the FPGA can complete configuration during the specified time.
Many third-party flash vendors do not meet these specific time constraints.
Single and Multiple Configuration Images
In most FPGA applications, the FPGA is loaded only when the system is powered on.
However, some applications reload the FPGA multiple times while the system is
operating, with different FPGA bitstreams for different functions. For example, the FPGA
can be loaded with one bitstream to implement a power-on self-test, followed by a second
bitstream with the final application. In many test equipment applications, the FPGA is
loaded with different bitstreams to execute hardware-assisted tests. In this way, one
smaller FPGA can implement the equivalent functionality of a larger ASIC or gate array
device.
See Chapter 7, Reconfiguration and MultiBoot, for more information.
MultiBoot /Safe Update
In advanced applications, multiple bitstream images can be stored. One of the images can
be upgraded by the user application, and real-time system upgrades can occur. The system
can also recover from any failure booting from the initial image.
Required I/O Voltages
The chosen FPGA configuration mode places some constraints on the FPGA application,
specifically the I/O voltage allowed on the FPGA's configuration banks.
For example, the SPI or BPI modes leverage third-party flash memory components that are
usually 3.3V-only devices (but tolerant to lower voltages). This requires that the I/O
voltage on the bank or banks attached to the memory must comply with the input voltage.
V
ccaux
Level
The V
ccaux
level is programmable as either 2.5V (default) or 3.3V. The user specifies the
value in the tools with the CONFIG VCCAUX=2.5 or CONFIG VCCAUX=3.3 constraint.
Nonvolatile Data Storage
Some FPGA applications store data in external nonvolatile memory. Spartan-6 FPGAs
provide useful enhancements for these applications.
• Spartan-6 FPGAs can configure directly from external commodity serial (SPI) or
parallel Flash PROMs (BPI).
• The Flash PROM address, data, and control pins are only borrowed by the FPGA
during configuration. After configuration, the FPGA has full read/write control over
these pins.
• The FPGA configuration bitstreams and the application’s nonvolatile data can share
the same PROM, reducing overall system cost.