User guide

18 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 1: Configuration Overview
The Slave SelectMAP mode is a simple x8- or x16-bit-wide processor peripheral interface,
including a chip-select input and a read/write control input. The Slave Serial mode is
extremely simple, consisting only of a clock and serial data input.
JTAG Connection
The four-wire JTAG interface is common on board testers and debugging hardware. In fact,
the Xilinx programming cables for Spartan-6 FPGAs, listed here, use the JTAG interface for
prototype download and debugging. Regardless of the configuration mode ultimately
used in the application, it is best to also include a JTAG configuration path for easy design
development. Also see Chapter 3, Boundary-Scan and JTAG Configuration.
• Platform Cable USB II
http://www.xilinx.com/products/devkits/HW-USB-II-G.htm
• Parallel Cable IV
http://www.xilinx.com/products/devkits/HW-PC4.htm
The Basic Configuration Solution
Basic options include either Master Serial mode using a Xilinx Platform Flash PROM or a
third-party SPI PROM. These solutions use the fewest FPGA pins, have flexible I/O
voltage support, and select SPI PROMs are supported by iMPACT, the Xilinx JTAG-based
programming software. See iMPACT Help under Software Help:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/isehelp_start.htm.
X-Ref Target - Figure 1-2
Figure 1-2: Slave Configuration Modes
DIN
CCLK
SERIAL_DATA
CLOCK
Spartan-6 FPGA
Processor,
Microcontroller
TDI
TMS
DATA_OUT
CLOCK
Spartan-6 FPGA
JTAG Tester,
Processor,
Microcontroller
TCK
TDO
MODE_SELECT
DATA_IN
D[7:0]
RDWR_B
CCLK
CSI_B
DATA[7:0]
SELECT
READ/WRITE
CLOCK
Spartan-6
FPGA
Processor,
Microcontroller
(c) Slave SelectMAP Mode
(a) Slave Serial Mode
(b) JTAG
UG380_c1_02_051109
Serial SelectMAP
8,16
D[15:8]DATA[15:8]