User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 17
UG380 (v2.7) October 29, 2014
Design Considerations
Slave Modes
The externally controlled loading FPGA configuration modes, generically called Slave
modes, are also available with either a serial or byte-wide datapath. In Slave mode, an
external “intelligent agent” such as a processor, microcontroller, DSP processor, or tester
downloads the configuration image into the FPGA, as shown in Figure 1-2. The advantage
of the Slave configuration modes is that the FPGA bitstream can reside almost anywhere in
the overall system. The bitstream can reside in flash, onboard, along with the host
processor's code. It can reside on a hard disk. It can originate somewhere over a network
connection or another type of bridge connection.
X-Ref Target - Figure 1-1
Figure 1-1: Master Configuration Modes
DATA[7:0]D[7:0]
FCS_B
Parallel NOR
Flash
D0
CLK
DIN
CCLK
Spartan-6 FPGA
DATA_IN
DATA_OUT
MOSI
CSO_B
SPI Serial
Flash
Xilinx
Platform Flash
PROM
SELECT
CLOCK
DIN
CCLK
ADDR[n:0]
CE#
A[n:0]
OE#
WE#
FOE_B
D[7:0]
CLK
D[7:0]
CCLK
Spartan-6 FPGA
(1)
Xilinx XCFxxP
Platform Flash
PROM
8
8/16
(a) Master Serial/SPI Mode
(b) Master Serial/SPI Mode with SPI Flash
(c) Master SelectMAP/BPI Mode
with Parallel NOR Flash
(d) Master SelectMAP/BPI Mode
n+1
UG380_c1_01_060109
XCFxxS
XCFxxP
XCFxxP
DATA[15:8]D[15:8]
Serial Byte-Wide
BYTE#LDC
Spartan-6 FPGA
Spartan-6 FPGA
FWE_B
Note: The remaining Spartan-6 FPGAs support XCFxxP Platform Flash PROMs via Master SelectMAP mode.
The master serial and the master SPI configuration modes are combined and use the same mode selection.
The master SelectMAP and the master BPI configuration modes are combined and use the same mode selection.