User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 169
UG380 (v2.7) October 29, 2014
JTAG Configuration/Readback
When the shutdown sequence is clocked by CCLK or UserCLK, the user is responsible for
knowing how many JTAGCLK cycles in Run/Test Idle are needed to complete the
shutdown sequence. The shutdown sequence is the startup sequence in reverse order.
Note:
When configuring the device through JTAG, the startup and shutdown clock should come
from TCK, regardless of the selection in BitGen.