User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 167
UG380 (v2.7) October 29, 2014
JTAG Configuration/Readback
Single Device Configuration
Table 10-4 describes the TAP controller commands required to configure a Spartan-6
device. Refer to Figure 10-2 for TAP controller states. These TAP controller commands are
issued automatically if configuring the part with the iMPACT software.
Table 10-4: Single Device Configuration Sequence
TAP Controller Step and Description
Set and Hold # of Clocks
TDI TMS TCK
1.
On power-up, place a logic 1 on the TMS, and clock the TCK five
times. This ensures starting in the TLR (Test-Logic-Reset) state.
X
1 5
2.
Move into the RTI state. X 0 1
3.
Move into the SELECT-IR state. X 1 2
4.
Enter the SHIFT-IR state. X 0 2
5.
Start loading the CFG_IN instruction, LSB first: 000101 0 5
6.
Load the MSB of CFG_IN instruction when exiting SHIFT-IR, as
defined in the IEEE standard.
0 1 1
7.
Enter the SELECT-DR state. X 1 2
8.
Enter the SHIFT-DR state. X 0 2
9.
Shift in the Spartan-6 FPGA bitstream. Bit
n
(MSB) is the first bit in
the bitstream
(1)
.
bit
1
... bit
n
0 (bits in bitstream)-1
10.
Shift in the last bit of the bitstream. Bit
0
(LSB) shifts on the
transition to EXIT1-DR.
bit
0
1 1
11.
Enter the UPDATE-DR state. X 1 1
12.
Move into the RTI state. X 0 1
13.
Enter the SELECT-IR state. X 1 2
14.
Move to the SHIFT-IR state. X 0 2
15.
Start loading the JSTART instruction. The JSTART instruction
initializes the startup sequence.
001100 0 5
16.
Load the last bit of the JSTART instruction. 0 1 1
17.
Move to the UPDATE-IR state. X 1 1
18.
Move to the RTI state and clock the startup sequence by applying
a minimum of 16 clock cycles to the TCK.
X
0 16
19.
Move to the TLR state. The device is now functional. X 1 3
Notes:
1. In the Configuration Register, data is shifted in from the right (TDI) to the left (TDO), MSB first. (Shifts into the Configuration
Register are different from shifts into the other registers in that they are MSB first.)