User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 163
UG380 (v2.7) October 29, 2014
JTAG Configuration/Readback
To invoke an operation, the desired opcode must be loaded into the Instruction Register
(IR). The length of the instruction register varies by device type. However, the IR is
6 bits wide for all Spartan-6 FPGAs.
Table 10-2: Spartan-6 FPGA Boundary-Scan Instructions
Boundary-Scan
Command
Instruction Description
EXTEST 001111 Enables boundary-scan EXTEST operation.
SAMPLE 000001 Enables boundary-scan SAMPLE operation.
USER1 000010 Access user-defined register 1.
USER2 000011 Access user-defined register 2.
USER3 011010 User code that allows fabric access to/from the TAP
controller from JTAG primitive instance 3.
USER4 011011 User code that allows fabric access to/from the TAP
controller from JTAG primitive instance 4.
CFG_OUT 000100 Access the configuration bus for readback.
CFG_IN 000101 Access the configuration bus for configuration.
INTEST 000111 Enables boundary-scan INTEST operation.
USERCODE 001000 Enables shifting out user code.
IDCODE 001001 Enables shifting out of ID code.
HIGHZ 001010 3-state output pins while enabling BYPASS Register.
JPROGRAM 001011 Equivalent to and has the same effect as PROGRAM.
JSTART 001100 Clocks the startup sequence when Startup clock source
is TCK (
StartupClk:JtagClk).
JSHUTDOWN 001101 Clocks the shutdown sequence.
ISC_ENABLE 010000 Marks the beginning of ISC configuration. Full
shutdown is executed.
ISC_PROGRAM 010001 Enables in-system programming.
ISC_NOOP 010100 No operation.
ISC_READ 010101 Used to read back battery-backed RAM.
ISC_DISABLE 010110 Completes ISC configuration. Startup sequence is
executed.
ISC_DNA
(ISC_FUSE_READ)
110000 Read Device DNA.
BYPASS 111111 Enables BYPASS.
RESERVED All other
codes
Xilinx reserved instructions.