User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 159
UG380 (v2.7) October 29, 2014
JTAG Configuration/Readback
The operation of each state is described here:
Test-Logic-Reset:
All test logic is disabled in this controller state, enabling the normal operation of the IC.
The TAP controller state machine is designed so that regardless of the initial state of the
controller, the Test-Logic-Reset state can be entered by holding TMS High and pulsing
TCK five times. Consequently, the Test Reset (TRST) pin is optional and not found on
Xilinx® devices.
Run-Test-Idle:
In this controller state, the test logic in the IC is active only if certain instructions are
present. For example, if an instruction activates the self test, then it is executed when the
controller enters this state. The test logic in the IC is idle otherwise.
Select-DR-Scan:
This controller state controls whether to enter the Datapath or the Select-IR-Scan state.
Select-IR-Scan:
This controller state controls whether or not to enter the Instruction Path. The controller
can return to the Test-Logic-Reset state otherwise.
Capture-IR:
In this controller state, the shift register bank in the Instruction Register parallel loads a
pattern of fixed values on the rising edge of TCK. The last two significant bits must always
be 01.
Shift-IR:
In this controller state, the instruction register gets connected between TDI and TDO, and
the captured pattern gets shifted on each rising edge of TCK. The instruction available on
the TDI pin is also shifted in to the instruction register.
Exit1-IR:
This controller state controls whether to enter the Pause-IR state or Update-IR state.
Pause-IR:
This state allows the shifting of the instruction register to be temporarily halted.
Exit2-DR:
This controller state controls whether to enter either the Shift-IR state or Update-IR state.
Update-IR:
In this controller state, the instruction in the instruction register is latched to the latch bank
of the Instruction Register on every falling edge of TCK. This instruction becomes the
current instruction after it is latched.
Capture-DR:
In this controller state, the data is parallel-loaded into the data registers selected by the
current instruction on the rising edge of TCK.
Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and
Update-IR states in the Instruction path.