User guide

150 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 9: Advanced Configuration Interfaces
If Readback is going to be performed on the device after configuration, the RDWR_B and
BUSY signals must be handled appropriately. (For details, refer to Chapter 6, Readback
and Configuration Verification.)
Otherwise, RDWR_B can be tied Low and BUSY can be ignored. The BUSY signal never
needs to be monitored when configuring Spartan-6 devices. Refer to Bitstream Loading
(Steps 4-7), page 83 and to Chapter 6, Readback and Configuration Verification.
Notes relevant to Figure 9-3:
1. The DONE pin is by default an open-drain output requiring an external pull-up
resistor. In this arrangement, the active DONE driver must be disabled.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3. The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
4. The BUSY signals can be left unconnected if readback is not needed.
5. An external controller such as a microprocessor or CPLD is needed to control
configuration.
6. The CCLK net requires Thevenin parallel termination. See Board Layout for
Configuration Clock (CCLK), page 54.
7. The data bus can be x8 or x16.
X-Ref Target - Figure 9-3
Figure 9-3: Multiple Slave Device Configuration on an 8-Bit SelectMAP Bus
PROGRAM
INIT
DONE
Spartan-6
FPGA
Slave
SelectMAP
INIT_B
D[7:0]
CCLK
RDWR_B
BUSY
CSI_B
PROGRAM_B
DONE
M1 M0
CS(1)
UG380_c9_03_052009
Spartan-6
FPGA
Slave
SelectMAP
INIT_B
D[7:0]
CCLK
RDWR_B
BUSY
CSI_B
DATA[7:0]
CCLK
WRITE
BUSY
PROGRAM_B
DONE
M1 M0
CS(0)
4.7 kΩ
330Ω
330Ω