User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 15
UG380 (v2.7) October 29, 2014
Chapter 1
Configuration Overview
Overview
Spartan®-6 FPGAs are configured by loading application-specific configuration data—a
bitstream—into internal memory. Spartan-6 FPGAs can load themselves from an external
nonvolatile memory device or they can be configured by an external smart source, such as
a microprocessor, DSP processor, microcontroller, PC, or board tester. In any case, there are
two general configuration datapaths. The first is the serial datapath that is used to
minimize the device pin requirements. The second datapath is the 8- or 16-bit datapath
used for higher performance or access (or link) to industry-standard interfaces, ideal for
external data sources like processors, or x8- or x16-parallel flash memory.
Like processors and processor peripherals, Xilinx® FPGAs can be reprogrammed, in
system, on demand, an unlimited number of times.
Because Xilinx FPGA configuration data is stored in CMOS configuration latches (CCLs), it
must be reconfigured after it is powered down. The bitstream is loaded each time into the
device through special configuration pins. These configuration pins serve as the interface
for a number of different configuration modes:
• JTAG configuration mode
• Master Serial/SPI configuration mode (x1, x2, and x4)
• Slave Serial configuration mode
• Master SelectMAP/BPI configuration mode (x8 and x16)
• Slave SelectMAP configuration mode (x8 and x16)
The configuration modes are explained in detail in Chapter 2, Configuration Interface
Basics.
The specific configuration mode is selected by setting the appropriate level on the mode
input pins M[1:0]. The M1 and M0 mode pins should be set at a constant DC voltage level,
either through pull-up or pull-down resistors (2.4 kΩ), or tied directly to ground or
VCCO_2. The mode pins should not be toggled during or before configuration but can be
toggled after. See Chapter 2, Configuration Interface Basics, for the mode pin setting
options.
The terms Master and Slave refer to the direction of the configuration clock (CCLK):
• In Master configuration modes, the Spartan-6 device drives CCLK from an internal
oscillator by default or optional external master clock source GCLK0/USERCCLK. To
select the desired frequency, the BitGen -g ConfigRate option is used for the
internal oscillator. The default is 2 MHz. The CCLK output frequency varies with
process, voltage, and temperature. The data sheet F
MCCKTOL
specification defines the
frequency tolerance. A frequency tolerance of ± 50% means that a ConfigRate setting
of 10 could generate a CCLK rate of between 5 MHz and 15 MHz.The BitGen section