User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 143
UG380 (v2.7) October 29, 2014
Post_CRC Constraints
• PRE_COMPUTED
BitGen calculates the CRC value and stores it in the FPGA. All CRC checks are
compared against this value (default).
•FIRST_READBACK
After successful configuration, the CRC logic runs in the FPGA and stores the first
calculated CRC value. All subsequent CRC checks are compared against this value.
POST_CRC_ACTION
POST_CRC_ACTION determines the behavior of the Readback CRC feature after a CRC
error is detected.
POST_CRC_ACTION can take two values:
•HALT
Once a CRC error is detected, do not perform any further readback CRC testing. After
the error is cleared, the CRC testing resumes (default).
•CONTINUE
Once a CRC error is detected, issue the error flag but continue to perform testing.
POST_CRC_FREQ
POST_CRC_FREQ determines the frequency of the internally generated clock to the
Readback CRC logic.
POST_CRC_FREQ can take these values: 2, 4, 6, 10, 12, 16, 22, 26, 33, 40, and 50.
These values do not directly represent a specific frequency. See the Spartan-6 FPGA Data
Sheet: DC and Switching Characteristics for the approximate frequency associated with each
of these values.
Syntax Examples
This section lists the supported syntax examples for each constraint.
POST_CRC
UCF Syntax Example
CONFIG POST_CRC = [ENABLE|DISABLE]
POST_CRC_INIT_FLAG
UCF Syntax Example
CONFIG POST_CRC_INIT_FLAG = [ENABLE|DISABLE]
POST_CRC_SOURCE
UCF Syntax Example
CONFIG POST_CRC_SOURCE = [PRE_COMPUTED|FIRST_READBACK]