User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 141
UG380 (v2.7) October 29, 2014
CRC Masking
CLBs Near Top or Bottom IOI DRP with LUTs Configured as
Distributed RAM
Using IOI with DRP in addition to LUTs configured as distributed RAM results in masking
that is a combination of the two scenarios above and results in five frames being masked,
as shown in Figure 8-3.
Readback CRC runs on different clock sources in different modes as indicated in Table 8-1.
X-Ref Target - Figure 8-3
Figure 8-3: CLB Masking with Both Distributed RAM and IOI DRP Enabled
SLICEM FramesSLICEX Frames
CLB CLB
14 CLBs
LUT6 LUT6
LUT6
LUT6LUT6
LUT6
LUT6LUT6
UG380_c8_03_052412
SLICEM
SLICEL
SLICEX
Top IOI
With
DRP
Top IOI
With
DRP
Table 8-1: Readback CRC Clock Sources
ICAP Primitive Master Modes Slave Modes JTAG Mode Clock Source
Instantiated x x x CLK input of the ICAP primitive
Not Instantiated Yes No No Internal oscillator with frequency constrained by
configuration constraint POST_CRC_FREQ
Not Instantiated No Yes No CCLK pin input
Not Instantiated No No Yes Internal oscillator with frequency constrained by
configuration constraint POST_CRC_FREQ