User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 139

UG380 (v2.7) October 29, 2014

CRC Masking

There are two types of CLBs, those containing SLICEM, which are able to configure as

distributed RAM, and those containing SLICEL, which cannot. SLICEM CLBs are the only

type that are masked in this scenario.

When a single LUT is configured as a distributed RAM, the 15 adjacent CLBs sharing the

same frame must be masked. Consequently, to maximize coverage of the CRC, it is

recommended to constrain LUTs configured as distributed RAM to frame boundaries. This

limits the amount of masking performed by BitGen and therefore increases the CRC

coverage.

X-Ref Target - Figure 8-1

Figure 8-1: CLB Frame Masking with Distributed RAM

Segments of four frames shown passing through

the LUTs of the two SLICEMs within a CLB

SLICEM FramesSLICEX Frames

CLB CLB

16 CLBs

LUT6

LUT6LUT6

LUT6

LUT6LUT6

UG380_c8_01_052412

SLICEM

SLICEL

SLICEX