User guide

138 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 8: Readback CRC
• In addition, the JTAG instruction register (IR) must not contain any configuration
instructions (CFG_IN, CFG_OUT, or ISC_ENABLE). When these instructions are
present, at any time, the readback CRC logic can not access the configuration logic
and cannot run. Any configuration operation performed via the JTAG interface
should finish by loading the IR with a value other than these three configuration
instructions.
These dynamically changeable memory locations are masked during background
readback:
• Look-up tables (LUTs) configured as distributed RAM or shift registers are not
checked. In Spartan-6 FPGAs, only SLICEMs can be configured as these memory
elements. Due to the granularity of the LUT masking, any LUTs in the same vertical
alignment as a LUTRAM or SRL16 in a given frame are not checked. To ensure
maximum coverage of the readback CRC, these LUTs used as memories must be kept
in separate frames from the LUTs used for logic.
• Block RAM content is dynamic, so it is not expected to be the same as the initial
configuration; therefore, these elements are not checked.
• Use of the PLL DRP is not masked; therefore, any change to the PLL results in a CRC
error.
• The I/O interface DRP at the top and bottom can be masked; however, LUTs for CLBs
in the same frame are also masked. Similarly, masking LUTs in the top or bottom
frame will also mask the I/O interface.
CRC Masking
Configuration data is organized into frames. Each frame of data configures portions of
multiple configurable logic blocks (CLBs), and multiple frames are needed to configure a
single CLB. The granularity of masking for the Spartan-6 FPGA is at a single frame that
spans several CLBs. To understand the coverage of the CRC, it is necessary to understand
the masking details. Three masking scenarios are presented:
• CLBs containing LUTs configured as distributed RAM
• CLBs near top or bottom IOI DRP
• CLBs near top or bottom IOI DRP with LUT configured as distributed RAM
Note:
Distributed RAM is a LUT configured as a distributed RAM or a shift register.
CLB with LUT Configured as Distributed RAM or Shift Register
Only the SLICEM contains LUTs capable of being configured as distributed RAM. The
architecture of Spartan-6 FPGAs pairs a SLICEM with a SLICEX in a CLB alternating with
a CLB comprised of a SLICEL with a SLICEX. For more information on CLB composition,
see UG384
, Spartan-6 FPGA Configurable Logic Block User Guide. A frame of data spans
16 CLBs, which includes 64 LUTs. For simplification, LUT6 (created using two LUT5
components) are shown in Figure 8-1 to demonstrate the frame data association with the
CLB.