User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 135
UG380 (v2.7) October 29, 2014
Status Register for Fallback and IPROG Reconfiguration
After the configuration logic receives the IPROG command, the FPGA resets everything
except the dedicated reconfiguration logic, and the INIT_B and DONE pins go Low. After
the FPGA clears all configuration memory, INIT_B goes High again. Then the value in
GENERAL1,2 is used for the bitstream starting address.
Status Register for Fallback and IPROG Reconfiguration
Spartan-6 devices contain a BOOTSTS that stores configuration history. At EOS or an error
condition, Status_0 is updated with the current status. If fallback or MultiBoot occurs,
Status_1 is updated at EOS or an error condition. The Valid_0 bit indicates if the rest of
Status_0 is valid or not. The BOOTSTS register is written either at an End Of Startup (EOS)
event or a fallback event. The EOS event happens after the first configuration attempt. A
successful MultiBoot operation via the IPROG command does not result in the BOOTSTS
register being updated. See Boot History Status Register (BOOTSTS), page 107.
Table 7-2 through Table 7-4 show the BOOTSTS values in some common situations.
Watchdog Timer
The Spartan-6 FPGA watchdog timer is used to monitor detection of the sync word. When
the watchdog timer times out, the configuration logic increments the strike count and
attempts to reconfigure if the BitGen option -g Reset_On_Err is Yes and the maximum
strike limit has not been reached. The Fallback MultiBoot section provides more details.
The watchdog timer uses the same clock source as the configuration clock. The watchdog
counter limit is configurable by setting the Configuration WatchDog Timer (CWDT)
Table 7-2: Status after First Bitstream Configuration without Error
CRC_ERROR ID_ERROR WTO_ERROR IPROG FALLBACK VALID
Status_1 0 0 0 0 0 0
Status_0 0 0 0 0 0 1
Table 7-3: First Configuration followed by IPROG
CRC_ERROR ID_ERROR WTO_ERROR IPROG FALLBACK VALID
Status_1 0 0 0 0 0 1
Status_0 0 0 0 1 0 1
Table 7-4: IPROG Embedded in First Bitstream, Second Bitstream CRC Error, and
Fallback Successfully
CRC_ERROR
(1)
ID_ERROR WTO_ERROR IPROG FALLBACK VALID
Status_1
(2)
000111
Status_0
(3)
100101
Notes:
1. CRC_Error only registers CRC errors detected during initial configuration. CRC_Error is not updated
if CRC errors are found from the Readback CRC (POST_CRC) function.
2. Status_1 shows a fallback bitstream was loaded successfully. The IPROG bit was also set in this case,
because the fallback bitstream contains an IPROG command. Although the IPROG command is
ignored during fallback, the status still records this occurrence.
3. Status_0 shows IPROG was attempted, and a CRC_ERROR was detected for that bitstream.