User guide

132 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 7: Reconfiguration and MultiBoot
Fallback MultiBoot
Fallback Behavior
Spartan-6 FPGAs have dedicated MultiBoot logic, which is used for both fallback and
MultiBoot (IPROG) reconfiguration. When fallback or IPROG happens, an internally
generated pulse resets the entire configuration logic, except for the dedicated MultiBoot
logic and the BOOTSTS, MODE, and GENERAL1.5 registers. See Figure 7-1. This reset
pulse pulls INIT_B and DONE Low, and restarts the configuration process by clearing
configuration memory.
During configuration, a CRC error or a watchdog timer time-out error can trigger fallback.
The watchdog timer is only active in master configuration modes. The time-out value is
user configurable using the BitGen -g TIMER_CFG switch. The switch is followed by a
16-bit value (greater than 16h'0201) indicating the number of configuration clocks
allowed before detection of the Sync word times out.
During fallback reconfiguration, the FPGA increments the strike count, stored in the
BOOTSTS register, and continues reconfiguration if the strike count is less than the limit
permitted for that image. If the limit is not reached, the FPGA checks the NEW_MODE bit
in the MODE register. If this value is 0, the device uses the configuration mode defined by
the mode pins. If the value is 1, the device uses the configuration mode defined in the
BOOTMODE bits in the MODE register. The NEW_MODE register is set by the BitGen
option -g Next_Config_New_Mode:Yes. The BOOTMODE bits are set by the BitGen
option -g Next_Config_Boot_Mode.
X-Ref Target - Figure 7-1
Figure 7-1: MultiBoot Logic
UG380_c7_01_051009
Strike 0..2
0xFFFFFF
0x000000
MultiBoot
Bitstream
Golden
Header
1st Image
2nd Image
3rd Image
Strike 3..5
Strike 6..8