User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 123
UG380 (v2.7) October 29, 2014
Readback Command Sequences
Configuration Memory Read Procedure (IEEE Std 1149.1 JTAG)
The process for reading configuration memory from the FDRO register through the JTAG
interface is similar to the process for reading from other registers. However, additional
steps are needed to accommodate frame logic. Configuration data coming from the FDRO
register pass through the frame buffer, therefore the first frame of readback data is dummy
data and should be discarded (refer to the FDRI and FDRO register description). The
IEEE Std 1149.1 JTAG readback flow is recommended for most users.
1. Reset the TAP controller.
2. Shift the CFG_IN instruction into the JTAG Instruction Register. The LSB of the
CFG_IN instruction is shifted first; the MSB is shifted while moving the TAP controller
out of the SHIFT-IR state.
3. Shift packet write commands into the CFG_IN register through the Shift-DR state:
a. Write a dummy word to the device.
b. Write the synchronization word to the device.
c. Write 1 word to CMD register header.
d. Specify the length of the data frame to be read back.
e. Write the starting frame address to the FAR registers.
4. Shift the JSHUTDOWN instruction into the JTAG Instruction Register.
5. Move into the RTI state; remain there for 24 TCK cycles to complete the Shutdown
sequence. The DONE pin goes Low during the Shutdown sequence.
6. Shift the CFG_IN instruction into the JTAG Instruction Register.
7. Move to the Shift-DR state and shift packet write commands into the CFG_IN register:
a. Write a dummy word to the device.
b. Write the synchronization word to the device.
c. Write 1 word to CMD register header.
d. Specify the length of the data frame to be read back.
e. Write the starting frame address to the FAR registers.
f. Write the RCFG command to the device.
g. Write the read FDRO register Type-1 packet header to the device.
h. Write two dummy words to the device to flush the packet buffer.
The MSB of all configuration packets sent through the CFG_IN register must be sent
first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.
8. Shift the CFG_OUT instruction into the JTAG Instruction Register through the
Shift-DR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted
while moving the TAP controller out of the SHIFT-IR state.
9. Shift frame data from the FDRO register through the Shift-DR state.
10. Reset the TAP controller.