User guide

120 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 6: Readback and Configuration Verification
User logic should strobe readback data while DOUT_BUSY is Low after switching from a
write to a read (both CSI_B and RDWR_B are Low). DOUT_BUSY must be monitored to
determine when the readback data is valid.
When readback is initiated, and after BUSY is deasserted, a number of dummy words
depending on the SelectMAP bus width are read prior to valid data behind present.
Table 6-3 lists the dummy readback cycles for the two SelectMAP widths.
Accessing Configuration Registers through the JTAG Interface
JTAG access to the Spartan-6 FPGA configuration logic is provided through the JTAG
CFG_IN and CFG_OUT registers. The CFG_IN and CFG_OUT registers are not
configuration registers, rather they are JTAG registers like BYPASS and
BOUNDARY_SCAN. Data shifted into the CFG_IN register goes to the configuration
packet processor, where it is processed in the same way commands from the SelectMAP
interface are processed.
Readback commands are written to the configuration logic by going through the CFG_IN
register; configuration memory is read through the CFG_OUT register. The JTAG state
transitions for accessing the CFG_IN and CFG_OUT registers are described in Table 6-4.
13 Write
30A1 Type 1 Write 1 Word to CMD
0005 START Command
2000 Type 1 NOOP Word 0
2000 Type 1 NOOP Word 0
2000 Type 1 NOOP Word 0
2000 Type 1 NOOP Word 0
14 Write
30A1 Type 1 Write 1 Word to CMD
0007 RCRC Command
2000 Type 1 NOOP Word 0
15 Write
30A1 Type 1 Write 1 Word to CMD
000D DESYNC Command
16 Write 2000
Type 1 NOOP Word 0
REPEAT for at least 16 cycles.
Table 6-2: Shutdown Readback Command Sequence (SelectMAP) (Cont’d)
Step SelectMAP Port Direction Configuration Data Explanation
Table 6-3: Readback Latency (SelectMAP)
x8 x16
CSI_B to Readback Latency 3 clocks 2 clocks
Notes:
1. These latencies assume CSI_B and RDWR_B are deasserted for one cycle between write and read. If
the deassertion lasts more than one cycle, then the latency is less. It is best to monitor the BUSY signal
for valid readback data.