User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 109
UG380 (v2.7) October 29, 2014
Default Initial Configuration Process
Default Initial Configuration Process
Initial configuration using a default bitstream (a bitstream generated using the default
BitGen settings) begins by pulsing the PROGRAM_B pin for SelectMAP and Serial
configuration modes or by issuing the JPROGRAM instruction for JTAG configuration
mode.
Spartan-6 FPGA Unique Device Identifier (Device DNA)
Spartan-6 FPGAs contain an embedded, unique device identifier (device DNA). The
identifier is nonvolatile, permanently programmed into the FPGA, and is unchangeable,
making it tamper resistant.
The FPGA application accesses the identifier value using the Device DNA Access Port
(DNA_PORT) design primitive, shown in Figure 5-13.
Table 5-50: Spartan-6 FPGA Bitstream Structure
Section Description Example
DUMMYWORD Sixteen dummy words for BPI address shift cycle. 0xFFFF
SYNC WORD Two word (32-bit) pattern for synchronization. 0xAA99
0x5566
HEADER Configuration register setup.
CFG BODY Starting address
R/W command
FDRI/FDRO
Configuration memory contents
AUTO CRC word
HEADER2 Configuration register setup (for daisy-chain and
features available after configuration).
CTL
DESYNC WORD One word (16-bit) pattern signifying the end of the
bitstream.
0x000D
Notes:
1. Configuration CRC calculation begins immediately after the SYNC WORD and the final check occurs
before the DESYNC WORD.
X-Ref Target - Figure 5-13
Figure 5-13: Spartan-6 FPGA DNA_PORT Design Primitive
UG380_c5_13_052009
DIN DOUT
READ
CLK
DNA_PORT
SHIFT