User guide

108 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
SEU_OPT Register
This register enables SEU detection and contains the status and frequency at which the
FPGA should run during SEU detection. Each bit position of the SEU_OPT register is
described in Table 5-49.
Bitstream Composition
Configuration can begin after the device is powered and initialization has finished, as
indicated by the INIT_B pin being released. After initialization, the packet processor
ignores all data presented on the configuration interface until it receives the
synchronization word. After synchronization, the packet processor waits for a valid packet
header to begin the configuration process. A bitstream for regular configuration has the
structure as shown in Table 5-50.
CRC_ERROR_0 5 CRC error.
ID_ERROR_0 4 IDCODE not validated while trying to write FDRI.
WTO_ERROR_0 3 Watchdog time-out error.
RESERVED 2 Reserved
FALLBACK_0 1 1: Fallback to golden bit stream address.
0: Normal configuration.
VALID_0 0 Status Valid.
Table 5-48: BOOTSTS Register Description (Cont’d)
Name Bits Description
Table 5-49: Soft Error Upset Option Register
Name Bits Description Default
RESERVED 15 Reserved. 1
RESERVED 14 Reserved. 0
SEU_FREQ 13:4 Bus_clk frequency during SEU
detection.
10x1be
SEU_RUN_ON_ERR 3 If SEU_ERR is detected, keep
running?
0: Halt.
1: Keep running.
0
GLUT_MASK 1 Mask out LUTRAM/SRL readback.
0: Unmask.
1: Mask out LUTRAM/SRL.
Also controlled by the BitGen
option -g glutmask.
1
SEU_ENABLE 0 Enable SEU Detection.
0: Disable.
1: Enable.
0