User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 107
UG380 (v2.7) October 29, 2014
Configuration Packets
CCLK_FREQ Register
PU_GWE Register
This 10-bit register stores the wake-up GWE sequence from suspend. See Table 5-46.
PU_GTS Register
This 10-bit register stores the wake-up GTS sequence from suspend. See Table 5-47.
Boot History Status Register (BOOTSTS)
This register is reset by POR or asserting PROGRAM_B. It is not reset by an IPROG
command, because the purpose of this register is to store the potential errors of a MultiBoot
operation. At EOS or an error condition, status (_0) is updated with the current status. If
fallback or MultiBoot occurs, status (_1) is updated at EOS or an error condition. BOOTSTS
is not updated after a successful IPROG command. The name of each bit position in the
BOOTSTS register is given in Table 5-48.
Table 5-45: Master Mode CCLK Frequency Select Description
Name Bits Description Default
EXT_MCLK 14 Select external master clock.
0: Select internal master clock.
1: Select external master clock.
0
MCLK_FREQ 9:0 CCLK frequency select. This register is a shared use
register with the ExtMCCLK_Divide signal, which
divides the external clock.
10x1BE
Table 5-46: Wake-Up 10-Bit Register Default
Bits [9:0]
Default Value 10h'006
Table 5-47: 10-Bit Wake-Up Register Default
Bits [9:0]
Default Value 10h'005
Table 5-48: BOOTSTS Register Description
Name Bits Description
STRIKE_CNT 15:12 Strike count.
CRC_ERROR_1 11 CRC error.
ID_ERROR_1 10 IDCODE not validated while trying to write FDRI.
WTO_ERROR_1 9 Watchdog time-out error.
RESERVED 8 Reserved.
FALLBACK_1 7 1: Fallback to 00 address.
0: Normal configuration.
VALID_1 6 Status Valid.