User guide

106 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
If it is a known-vendor command, the SPI read command needs to be loaded to
GENERAL2.
In case of SPI, the general register contains an 8-bit command plus a 24-bit address. See
Table 5-42.
BPI has a 26-bit address (there are 6 don’t care bits). See Table 5-43.
MODE Register
The MODE register contains the mode setting (two bits for bus width, three bits for mode,
and eight bits for vsel), which can be used for the reboot. The default is the original pin
setting.
This register is cleared in the same way as General registers, that is they can only be cleared
by bus_reset0 but NOT by reboot_rst (bus_reset = bus_reset || reboot_rst). See
Table 5-44.
Table 5-42: SPI General Register Example
gen2[15:0] gen1[15:0]
rd_cmd[7:0], addr[23:16] addr[15:0]
Table 5-43: BPI General Register Example
gen2[15:0] gen1[15:0]
xxxxxx, address[25:16] addr[15:0]
Table 5-44: MODE Registers Description
Name Bits Description Default
RESERVED 15 Reserved. 0
RESERVED 14 Reserved. 0
NEW_MODE 13 0: Physical mode, ignore bit[10:0] (default).
1: Bitstream mode, use bit[10:0], required for
MultiBoot and Fallback.
0
BUSWIDTH 12:11 The buswidth setting to reboot.
SPI:
00: by 1
01: by 2
10: by 4
00 (SPI by1)
BOOTMODE 10:8 Mode setting required for MultiBoot and
Fallback. Enabled by NEW_MODE.
bit [10]: Reserved
bit [9]: BOOTMODE <1>
bit [8]: BOOTMODE <0>
001
BOOTVSEL 7:0 The vsel setting to reboot. Read only.