User guide

104 www.xilinx.com Spartan-6 FPGA Configuration User Guide
UG380 (v2.7) October 29, 2014
Chapter 5: Configuration Details
Suspend Register (PWRDN_REG)
Frame Length Register
Frame Length Register (FLR) is written with the length of a frame, as measured in 16-bit
words, near the beginning of the configuration bitstream. FLR must be written before any
FDR operation will work. It is not necessary to set the FLR more than once.
The actual value written to FLR = Actual Frame Length.
Based on the segmentation scheme in Spartan-6 devices, the frame length for type0 (CLB,
IOI, and special blocks) and type1 (block RAM) are fixed. The only block that needs a
specified frame length is IOB.
Multi-Frame Write Register
The Spartan-6 FPGA supports Multi-Frame Write (MFWR) for first-time configuration but
does not support it during reconfiguration. The FPGA has to go through one power cycle
or use PROGRAM_B to reset the chip before MFWR can be used.
Table 5-37: Power-Down Register Description
Field Bit Index Description BitGen Default
RESERVED 15 Reserved.
EN_EYES 14 Enable Multi-Pin Wake-Up.
0: Disable Multi-Pin Wake-Up.
1: Enable Multi-Pin Wake-Up.
0
RESERVED 13:6 Reserved. 0010_0010
FILTER_B 5 0: Suspend filter (300 ns) on.
1: Filter off.
0
EN_PGSR 4 0: No GSR pulse during return from Suspend.
1: Generate GSR pulse during return from
Suspend.
0
RESERVED 3 Reserved.
EN_PWRDN 2 0: Suspend is disabled.
1: Suspend is enabled.
0
KEEP_SCLK 0 0: Use MCCLK for startup sequence initiated
by power-up.
1: Use SSCLKSRC for startup sequence
initiated by power-up.
1
Table 5-38: Frame Length Register
Bits FLR
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