User guide

Spartan-6 FPGA Configuration User Guide www.xilinx.com 103
UG380 (v2.7) October 29, 2014
Configuration Packets
Configuration Options Register (COR1 and COR2)
The Configuration Options Register is used to set certain configuration options for the
device. The name of each bit position in COR1 and COR2 is given in Table 5-36.
Table 5-36: Configuration Options (COR1 and COR2) Descriptions
Register Field Bit Index Description BitGen Default
COR1 DRIVE_AWAKE
15
0: Does not drive the awake pin (open drain).
1: Actively drives the awake pin.
0
RESERVED 14:5 Reserved. 0110111000
CRC_BYPASS 4 Does not check against the updated CRC value. 0
DONE_PIPE 3 0: No pipeline stage for DONEIN.
1: Add pipeline stage to DONEIN.
0
DRIVE_DONE 2 0: DONE pin is open drain.
1: DONE pin is actively driven High.
0
SSCLKSRC 1:0 Startup sequence clock.
00: CCLK.
01: UserClk.
1x: TCK.
00
COR2 RESET_ON_ERROR 15 Option to fallback when a crc_error occurs.
0: Disable reset on error.
1: Enable reset on error.
0
RESERVED 14:12 Reserved 000
DONE_CYCLE 11:9 Startup phase in which DONE pin is released.
(001,010,011,100,101,110)
100
LCK_CYCLE 8:6 Stall in this startup phase until DCM or PLL lock is
asserted. (001,010,011,100,101,110,111<No
wait>)
111 (No wait)
GTS_CYCLE 5:3 Startup phase in which I/Os switch from 3-state to user
design.
(000<Keep>, 001,010,011,100,101,110,
111<Done>)
101
GWE_CYCLE 2:0 Startup phase in which the global write enable is asserted.
(000<Keep>, 001,010,011,100,101,110,
111<Done>)
110