Service manual

4. BOARD/UNIT DESCRIPTION
4.4 Service Manual BSM-4100
b) Display control block
The display control block consists of the dedicated graphic ASIC IBIS for entire
display control, two 8 MB DRAMs for display of waveform and graphic data, 512
KB high-speed SRAM for display of alphanumeric data and display interfaces for
the LCD and an external RGB monitor.
When the IBIS receives a display control command from the host CPU, the IBIS
accesses these memories to get the display data and arranges the display data for
RGB outputs. There are two RGB outputs. One is RGB output for the LCD through
the LVDS (Low Voltage Differential Signaling) interface. The other one is RGB
output for a locally available RGB monitor. The LVDS interface which is different
from a CMOS or TTL display interface uses approx. 0.3 V peak-to-peak differential
signal in serial data communication.
Host CPU
IBIS
LCD
LVDS buffer and interface
Graphic DRAM
8 MB x 2
Character SRAM
512 KB
D to A
AUX
(for analog RGB display)
c) Recorder control block
The recorder control block consists of the local CPU (16 MHz MC68SEC000), 1
MB system ROM for program storage, 512 KB system RAM for the local CPU
working area and the dedicated recorder control ASIC RACOON.
The local CPU accesses the ROM or RAM through the RACOON. When the
RACOON receives a recorder control command from the local CPU, the RACOON
accesses the RAM to get the recording data and controls all the recording
functions such as the motor and thermal array head in the recorder unit.
When the instrument is upgraded, the local bus in the recorder control block is
directly connected to the system bus (in the system control block) and the 1 MB
system ROM takes a part of the memory for the upgrade program.