Install guide

ManualsBrandsAUSTRALIAN MONITOR ManualsComputer equipmentXDS12

ARMY TM 5-6675-308-34

MARINE CORPS TM 08837A-34/2

frames, during three of which no synchro or resolver

conversions are made, the entire sequence repeats itself.

The A/D converter is contained on the A/D converter

circuit card assembly.

(8)

Platform input/output logic.

The platform 1/0

logic accumulates the AV pulses from the platform and

generates gyro torquing pulses

x, w

, and w

for the

platform. The platform I/O logic is contained on the

platform circuit card assembly.

(a)

accumulation.

Three AV accumulation

channels are provided. Each channel has an eight-bit,

up/down counter for the accumulation of velocity

pulses. Accumulation is provided by strobing each

channel at the 2.4-kHz quantizer clock rate into its

individual flip-flop, thereby providing a one-bit sample

for each channel. Synchronization to the basic CPU

clock is implemented to eliminate any hazardous logic

condition before sampling. Special logic is implemented

to inhibit counters from toggling during a program

input command of any accumulated velocity data. The

leading edge of the quantizer clock initiates the one-bit

accumulation process. The contents of the AV counters

are read under software control.

(b) Gyro torguing. The platform I/O provides

three channels of gyro torquing pulses. Each gyro chan-

nel has its own eight-bit up/down counter and is indi-

vidually loaded with torque data under software control

and then is either increased or decreased at gyro torque

rate, providing full rate torquing. Periodic update under

software control updates each counter.

(9) Serial data bus. The SDB functions as a bidi-

rectional communications link between the computer

and various external devices. The SDB consists of a data

envelope, address evelope, bidirectional data line, and a

continuous 250-kHz clock. All serial communications

are completely under programmed I/O control. To

initiate a serial transfer, an address word is transmitted

to all devices using an OUT 12 instruction. All address

words contain a device code (bits 0-2), a transmit/

receive bit (bit 3), and a self-test bit (bit 4). The balance

of the 16 bits in the address word are a unique function

of each device. Data is transmitted to a device using an

OUT 11. Data is transmitted from a device to the

computer using an INP 11 to command a serial transfer

into the I/O shift register. This INP 11 results in the

accumulator receiving the complement of the previ-

ously transmitted computer word and can be used as a

short-loop self-test feature. A second INP 11 transfers

the contents of the shift register to the CPU. A mini-

mum delay of 84 microseconds is required between

program commands to the serial I/O. A discrete bit

may be read by the computer to determine the results

of a parity test on received words and the serial bus

logic may be checked for its busy state. The serial data

bus logic is contained on the data buffer circuit card

assembly.

(10)

Input/output discrete, lamp dimmer control,

and on/off control.

(a) Input discretes. The following inputs are

received and made available for program access: IMU

ready, accelerometer coarse heater on, gyro coarse

heater on, gyro float to temperature, and IMU spares

no. 1, 2, and 3. In addition, the IMU fail discrete is

received for processing but is not available to the

software.

(b)

Output discretes.

The following outputs are

processed by the computer from software for subse-

quent transmission to other system elements: PS flag

set, CDU flag set, IMU flag set, computer flag set, reset

all flags, XY gyro fast slew, and Z gyro fast slew. A

power-on-reset signal is also made available.

control is a four-bit non-linear digital/analog converter

whose outputs, under software control, are used to

control the lamp voltage to the CDU. For each of ten

binary codes, a unique analog voltage is generated.

(d) On/off control. Computer tumon occurs

when + 24V input power is applied. Power turnoff

control has three modes of operation. Each of these

modes generates an off command to the power supply

and a power off interrupt to the CDU. An overtempera-

ture condition in the computer will generate an off

command. The software is also capable of generating an

off command. Normal shutdown occurs when the on/

off input is activated and is followed by an enter

command.

e. Computer Power Supply. The computer power

supply receives unregulated + 24V from the power

supply and generates

+ 5V, + 15V, and –15V for

computer operation. See figure 2-2 for a functional

block diagram of the computer power supply. In addi-

tion, the computer power supply supplies a variable

voltage for the CDU display lamps and necessary con-

trol signals for the PS and computer. The computer

power supply consists of the following major elements:

+ 5V switching regulator

O to + 5V switching regulator

+ 15V switching regulator

Dc-todc converter

+ 15V precision supply

–15V precision supply

Control and monitor section

(1) +5 V switching regulator. The + 5V switching

regulator is located on the 5V power supply circuit

card assembly. The + 5V switching regulator develops

+ 5V with input variations of +20 to + 30V and with

load variations of 3 to 18 amps. In addition to the

filtered + 24V unregulated input power, the + 5V

2-7