Install guide

ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
contents of the memory register are then presented to
the adder unit input through the B-switch along with no
input (zero) from the A-switch. The output of the adder
unit, representing the operand is then strobed into the
accumulator. For the case where a 32-bit transfer is
executed, two 16-bit operands are sequentially strobed
into the memory register. Upon completion of two
memory cycles, a full 32-bit operand is loaded into the
accumulator.
d Input/Output Section The I/O section provides
an interface between the CPU and memory and devices
external to the computer. The I/O section is contained
on I/O controller card assembly, data buffer circuit
card assembly, I/O discrete circuit card assembly, ana-
log-to-digital (A/D) converter circuit card assembly,
and platform I/O circuit card assembly, and consists of
the following major elements:
Programmed input/output control
DMA control
Interrupt control and masks
Real-time counter
Data bus buffer
Time-out counter
A/D converter
Platform I/O logic
Serial data bus
I/O discrete, lamp dimmer control, and on/off control
(1) Programmed input/output control. Program-
ed I/O refers to the communication of information
between the CPU and the various external devices and
is initiated by the operational program. Programmed
I/O is performed by the execution of instructions which
input to or output from the CPU accumulator. The
four-bit device address field in these instructions enables
direct communication with 16 devices. Address decod-
ing and control signal generation for the external de-
vices is performed by the I/O controller card assembly.
(2) DMA control DMA control provides a trans-
fer of data between the memory and an external device
with CPU involvement. In this mode of operation,
memory cycles are obtained from the CPU by the
external device which generates the address for the
memory location to be a accessed on a request-response
basis. The computer contains logic for eight DMA
channels but only one is used. Channel two is used for
the A/D conversion.
(3) Interrupt control and masks. The interrupt
control and masks provide interface between the CPU
and I/O section for the three separately addressable and
independent hardware interrupts. These interrupt func-
ions are priority, service, and internal. No dedicated
addresses in memory are required for these interrupts,
thereby allowing complete relocatibility of the associ-
ated subroutines. When an interrupt signal occurs,
other interrupts are logically inhibited or masked out.
The interrupt control and masks are contained on the
I/O controller card assembly.
(a) Priority interrupt. A priority interrupt is
generated by the time-out counter and just prior to
power shutdown. The time-out counter will oveflow if
it is not reset at least once every 125 milliseconds, The
overflow will generate a priority interrupt. A priority
interrupt is generated one millisecond prior to com-
puter power shutdown to permit the software to save
any required data.
(b) Service interrupt. A service interrupt is gen-
erated when the real-time counter overflows.
(c) Internal interrupt. The internal interrupt is
generated by an overflow or divide fault condition and
is associated with the status register. Bit position 0 of
the status register identifies an overflow and bit 1 a
divide fault.
(4) Real-time counter. The real-time counter is a
hardware counter loadable and readable by the CPU; it
aids the program in determining the time between
events. In addition the real-time counter has an over-
flow function that is used to generate the service inter-
rupt. The real-time counter is contained on the I/O
controller card assembly.
(5) Data bus buffer. The data bus buffer provides
buffering of the data bus between the I/O section and
CPU. This buffering is required because of the loading
in excess of the drive capability provided by the CPU,
The data bus buffer is contained on the data buffer
circuit card assembly.
(6) Time-out counter. The time-out counter is a
four-bit counter which generates a priority interrupt
when it overflows. This counter is periodically reset by
the software so that a software failure is indicated if an
overflow does occur and the bit indicator is set.
(7)
Analog-to-digital converter. All analog signals
are routed through the A/D converter before process-
ing by the CPU. The A/D converter converts analog
signals from the I MU into digital signals for subsequent
processing. The A/D converter generates its basic tim-
ing reference from positive-going crossovers of the 400-
Hz reference. Each crossover initiates a timing frame in
which all the DC-to-digital signals and one of the
resolver or synchro signals is converted. The synchro or
resolver signal is the first conversion within the frame
and is then followed by all the dc signals. Conversion of
the resolver or synchro signal occurs at the time frame
which compensates for the phase shift for that particu-
lar signal. In this manner, conversions occur at the
signal peaks and quadrature effects are minimized. After
each signal is converted, a DMA cycle is initiated and
the converted value is stored into memory. After eight
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