Install guide

ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
(h) Bus and switch controls. The bus and switch
controls provide the switching for the DMA and inter-
rupt control, The output of the bus and switch controls
is routed to the output switch for switching onto the
SDB.
b. Core Memory.
The core memory contains the
timing and registers required for storing data in the
core stack assembly. The data loop circuit card assem-
bly, drive circuit card assembly, and core stack assembly
make up the memory. The memory consists of the
following major elements:
Memory buffer register
Memory address register
Sense inhibit functions
Core stack assembly
(1) Memory buffer
register. The memory buffer
register is used to store the output of the memory
during read operations and holds the input to memory
storage during write operations. The memory buffer
register is 16 bits to handle a 16-bit operand or instruc-
tion. Two memory cycles are required for 32-bit oper-
ands.
(2) Memory address register. The memory address
register contains the address of the requested location in
memory. The address may be an instruction address, an
operand address, or an indirect address. The contents of
the memory location addressed in turn may contain an
instruction, operand or another address.
(3) Sense inhibit functions. Data storage and re-
trieval are accomplished by the inhibit drivers and sense
amplifiers. When data is to be accessed from an ad-
dressed location, the contents of the selected location
are sensed via the sense inhibit wire and applied to the
sense amplifiers. The sense amplifiers then feed the
information into the memory buffer register. One
group, of 16 bits, of the memory address register is then
enabled and the data is sent to the CPU or input/
output section via the SDB. When data is to be stored
into an addressed location, the contents of the SDB
(from the CPU or I/O section) are strobed into the
memory buffer register.
The selected 16 bits of the
memory address register are then fed to the inhibit
drivers and the data is written into the addressed loca-
tion.
(4) Core stack assembly. The core stack assembly
is organized in a conventional 3-wire coincident current
manner with a storage capacity of 32,768 words. The
memory word length is 16 bits.
b.1 So/id State Memory. The solid state memory
contains the timing and registers required for storing
data. The single card assembly memory consists of the
following major elements:
Memory buffers
Memory address register
Memory
(1) Memory buffers.
Separate input and output
buffers are used, each 16 bits wide. The input buffer
holds data at the memory during write cycles and the
output buffer drives memory data onto the data bus
during read cycles. A 16-bit operand or instruction
takes a single cycle while 32-bit operands require two.
(2) Memory address register. The memory address
register contains the address of the requested location in
memory. The address is latched at the beginning of a
cycle and held stable while the memory is being ac-
cessed. The location addressed can contain an instruc-
tion, operand or another address.
(3) Memory. The memory is partitioned in 48K
words of nonvolatile EEPROM and 16K words of static
ram. The EEPROM retains program instructions and
constants when power is removed and can be updated
by the computer within the system. The ram provides a
read/write scratchpad for data.
c. Data Flow Orientation. A common bidirectional
data and address bus is used to establish orderly com-
munication between the memory CPU, I/O section, and
test devices. Each device on the bus is controlled by the
CPU. Top priority is given to the I/O section in order
to enhance DMA. When the memory is in use, the CPU
is still able to execute instructions which do not require
continuous memory access,
such as the multiply, shift
and divide instructions.
(1) Operation within the data section revolves
around use of a central adder unit. The inputs to the
adder unit are from the B-switch and the A-switch. The
output of the adder unit services all registers. In addi-
tion, the adder unit also services the memory address
register and memory buffer register in the memory. For
the memory registers, the adder unit supplies both the
effective addresses and data to be stored on the same 16
lines of the output switch to the memory.
(2) During an instruction fetch cycle, the instruc-
tion is received from the memory buffer register
through the common bus
and strobed into the instruc-
tion register. In a memory reference instruction, the D
field modifies the address contained in the register
designated by the R field code, and the augmented
address is sent to the memory address register via the
output switch for the operand fetch cycle.
(3) Assuming that a single length load accumula-
tor instruction is in the instruction register, the operand
fetch results in 16 bits of data being placed in the
memory registers from the memory buffer register. The
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